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Searched refs:FP_ROUND (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def62 DAG_INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
H A DVPIntrinsics.def515 HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND, 1)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h897 FP_ROUND, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp3050 return DAG.getNode(ISD::FP_ROUND, DL, ScalarVT, Res, in PromoteReduction()
3271 case ISD::FP_ROUND: { in ExpandNode()
3344 Op = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
3729 DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4888 case ISD::FP_ROUND: in ConvertNodeToLibcall()
5307 TruncOp = ISD::FP_ROUND; in PromoteNode()
5316 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
5376 Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1, in PromoteNode()
5444 DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp3, in PromoteNode()
5473 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp118 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
1005 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
1056 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
1246 DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), Val, in SoftenFloatOp_STORE()
2078 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
2188 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2646 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2949 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, in PromoteFloatRes_XINT_TO_FP()
3035 case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break; in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp60 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
428 return DAG.getNode(ISD::FP_ROUND, DL,
785 case ISD::FP_ROUND: in ScalarizeVectorOperand()
965 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
1188 case ISD::FP_ROUND: in SplitVectorResult()
2479 if (Opcode == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
3151 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
4099 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
4184 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
4185 Hi = DAG.getNode(ISD::FP_ROUND, D in SplitVecOp_FP_ROUND()
[all...]
H A DLegalizeVectorOps.cpp427 case ISD::FP_ROUND: in LegalizeOp()
695 case ISD::FP_ROUND: in Promote()
737 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, in Promote()
H A DSelectionDAGDumper.cpp383 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
H A DDAGCombiner.cpp1937 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
13213 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
13239 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
17375 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
17379 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); in visitFDIV()
17548 N1.getOpcode() != ISD::FP_ROUND) in CanCombineFCOPYSIGN_EXTEND_ROUND()
17902 DAG.FoldConstantArithmetic(ISD::FP_ROUND, SDLoc(N), VT, {N0, N1})) in visitFP_ROUND()
17910 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
17915 if (!hasOperation(ISD::FP_ROUND, VT)) in visitFP_ROUND()
17936 ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2735 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1 }, in getCastInstrCost()
2736 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1 }, in getCastInstrCost()
2737 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3 }, in getCastInstrCost()
2740 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 }, in getCastInstrCost()
2741 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3 }, in getCastInstrCost()
2742 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7 }, in getCastInstrCost()
2745 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 }, in getCastInstrCost()
2746 { ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3 }, in getCastInstrCost()
2747 { ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6 }, in getCastInstrCost()
H A DAArch64ISelLowering.cpp589 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in AArch64TargetLowering()
590 setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom); in AArch64TargetLowering()
592 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
593 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
859 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Custom); in AArch64TargetLowering()
860 setOperationAction(ISD::FP_ROUND, MVT::v4bf16, Custom); in AArch64TargetLowering()
1206 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1612 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1701 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom); in AArch64TargetLowering()
1707 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp594 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
595 {ISD::FP_ROUND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
634 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
640 {ISD::FP_ROUND, MVT::v2f64, 2}, in getCastInstrCost()
828 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp193 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
2584 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2625 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2669 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2899 case ISD::FP_ROUND: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2666 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2711 return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, in LowerFLOGCommon()
2846 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
2996 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
3372 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerUINT_TO_FP()
3385 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
3418 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerSINT_TO_FP()
3434 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
4911 case ISD::FP_ROUND: { in performFNegCombine()
4916 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
[all …]
H A DR600ISelLowering.cpp201 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
1723 case ISD::FP_ROUND: { in PerformDAGCombine()
H A DSIISelLowering.cpp223 setOperationAction(ISD::FP_ROUND, MVT::bf16, Expand); in SITargetLowering()
284 setOperationAction(ISD::FP_ROUND, in SITargetLowering()
599 setOperationAction({ISD::FP_ROUND, ISD::STRICT_FP_ROUND, ISD::FCOS, in SITargetLowering()
926 setTargetDAGCombine(ISD::FP_ROUND); in SITargetLowering()
5801 case ISD::FP_ROUND: in LowerOperation()
6667 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
6681 if (Op.getOpcode() != ISD::FP_ROUND) in lowerFP_ROUND()
10583 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
10974 return DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Sqrt, in lowerFSQRTF16()
11232 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt, in performUCharToFloatCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1901 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1929 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1930 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3285 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1123 case ISD::FP_ROUND: in PreprocessISelDAG()
1137 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1352 case ISD::FP_ROUND: in PreprocessISelDAG()
1383 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
H A DX86ISelLoweringCall.cpp1162 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, in LowerCallResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1241 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1242 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1292 setOperationAction(ISD::FP_ROUND, VT, Custom); in PPCTargetLowering()
8941 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
9022 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
9319 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
11861 case ISD::FP_ROUND: in LowerOperation()
14727 DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, In.getOperand(0), in combineElementTruncationToVectorTruncation()
14772 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
14789 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND) in combineBVOfConsecutiveLoads()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp185 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
188 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
1578 : DAG.getNode(ISD::FP_ROUND, dl, ResTy, VecV, in resizeToWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1081 case ISD::FP_ROUND: { in getCastInstrCost()
H A DRISCVISelLowering.cpp467 setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom); in RISCVTargetLowering()
970 // RVV has native FP_ROUND & FP_EXTEND conversions where the element type in RISCVTargetLowering()
974 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1063 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1099 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1311 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
6479 return DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, Powi, in LowerOperation()
6508 case ISD::FP_ROUND: { in LowerOperation()
6518 DAG.getNode(ISD::FP_ROUND, DL, MVT::f32, Op0, in LowerOperation()
6544 return DAG.getNode(ISD::FP_ROUND, D in LowerOperation()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1806 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp787 setOperationAction(ISD::FP_ROUND, VT, Custom); in NVPTXTargetLowering()
2644 ISD::FP_ROUND, Loc, MVT::bf16, in LowerINT_TO_FP()
2794 case ISD::FP_ROUND: in LowerOperation()

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