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Searched refs:FP_ROUND (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp3089 {ISD::FP_ROUND, MVT::bf16, MVT::f32, 1}, // bfcvt in getCastInstrCost()
3090 {ISD::FP_ROUND, MVT::bf16, MVT::f64, 1}, // bfcvt in getCastInstrCost()
3091 {ISD::FP_ROUND, MVT::v4bf16, MVT::v4f32, 1}, // bfcvtn in getCastInstrCost()
3092 {ISD::FP_ROUND, MVT::v8bf16, MVT::v8f32, 2}, // bfcvtn+bfcvtn2 in getCastInstrCost()
3093 {ISD::FP_ROUND, MVT::v2bf16, MVT::v2f64, 2}, // bfcvtn+fcvtn in getCastInstrCost()
3094 {ISD::FP_ROUND, MVT::v4bf16, MVT::v4f64, 3}, // fcvtn+fcvtl2+bfcvtn in getCastInstrCost()
3095 {ISD::FP_ROUND, MVT::v8bf16, MVT::v8f64, 6}, // 2 * fcvtn+fcvtn2+bfcvtn in getCastInstrCost()
3210 {ISD::FP_ROUND, MVT::f32, MVT::f64, 1}, // fcvt in getCastInstrCost()
3211 {ISD::FP_ROUND, MVT::v2f32, MVT::v2f64, 1}, // fcvtn in getCastInstrCost()
3212 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 2}, // fcvtn+fcvtn2 in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp603 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in AArch64TargetLowering()
604 setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom); in AArch64TargetLowering()
606 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
607 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
896 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Custom); in AArch64TargetLowering()
897 setOperationAction(ISD::FP_ROUND, MVT::v4bf16, Custom); in AArch64TargetLowering()
1258 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1706 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1758 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1830 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def62 DAG_INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
H A DVPIntrinsics.def487 HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h941 FP_ROUND, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp3080 return DAG.getNode(ISD::FP_ROUND, DL, ScalarVT, Res, in PromoteReduction()
3302 case ISD::FP_ROUND: { in ExpandNode()
3375 Op = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
3868 DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
5095 case ISD::FP_ROUND: in ConvertNodeToLibcall()
5518 TruncOp = ISD::FP_ROUND; in PromoteNode()
5526 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
5586 Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1, in PromoteNode()
5656 DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp3, in PromoteNode()
5706 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
[all …]
H A DLegalizeVectorOps.cpp441 case ISD::FP_ROUND: in LegalizeOp()
704 DAG.getNode(ISD::FP_ROUND, DL, Node->getValueType(0), Rdx, in PromoteFloatVECREDUCE()
749 case ISD::FP_ROUND: in Promote()
812 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, in Promote()
1875 Result = DAG.getNode(ISD::FP_ROUND, DL, DstVT, UIToFP, TargetZero); in ExpandUINT_TO_FLOAT()
H A DLegalizeFloatTypes.cpp124 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
1147 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
1201 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
1391 DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), Val, in SoftenFloatOp_STORE()
2294 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
2404 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2891 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
3227 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, in PromoteFloatRes_XINT_TO_FP()
3313 case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break; in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp60 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
436 return DAG.getNode(ISD::FP_ROUND, DL, in ScalarizeVecRes_FP_ROUND()
798 case ISD::FP_ROUND: in ScalarizeVectorOperand()
1012 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
1236 case ISD::FP_ROUND: in SplitVectorResult()
2612 if (Opcode == ISD::FP_ROUND || Opcode == ISD::AssertNoFPClass) { in SplitVecRes_UnaryOp()
3423 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
4408 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
4485 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
4486 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
[all …]
H A DSelectionDAGDumper.cpp403 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
H A DDAGCombiner.cpp1998 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
14073 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
14099 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
18375 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
18379 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); in visitFDIV()
18549 N1.getOpcode() != ISD::FP_ROUND) in CanCombineFCOPYSIGN_EXTEND_ROUND()
18865 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FP_ROUND, DL, VT, {N0, N1})) in visitFP_ROUND()
18873 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
18878 if (!hasOperation(ISD::FP_ROUND, VT)) in visitFP_ROUND()
18898 ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
[all …]
H A DSelectionDAG.cpp1473 : getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtendOrRound()
5779 case ISD::FP_ROUND: { in isKnownNeverNaN()
6373 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
7262 if (N1CFP && Opcode == ISD::FP_ROUND) { in foldConstantFPMath()
7634 case ISD::FP_ROUND: in getNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp614 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
615 {ISD::FP_ROUND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
654 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
660 {ISD::FP_ROUND, MVT::v2f64, 2}, in getCastInstrCost()
848 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2723 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2768 return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, in LowerFLOGCommon()
2903 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
3054 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
3430 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerUINT_TO_FP()
3443 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
3476 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerSINT_TO_FP()
3492 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
5145 case ISD::FP_ROUND: { in performFNegCombine()
5150 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
[all …]
H A DSIISelLowering.cpp230 setOperationAction(ISD::FP_ROUND, MVT::bf16, Expand); in SITargetLowering()
291 setOperationAction(ISD::FP_ROUND, in SITargetLowering()
615 setOperationAction({ISD::FP_ROUND, ISD::STRICT_FP_ROUND, ISD::FCOS, in SITargetLowering()
937 setOperationAction(ISD::FP_ROUND, {MVT::bf16, MVT::v2bf16}, Custom); in SITargetLowering()
942 setOperationAction(ISD::FP_ROUND, in SITargetLowering()
994 setTargetDAGCombine(ISD::FP_ROUND); in SITargetLowering()
6160 case ISD::FP_ROUND: in LowerOperation()
7018 : DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
7059 if (Op.getOpcode() != ISD::FP_ROUND) in lowerFP_ROUND()
7069 SDValue Src32 = DAG.getNode(ISD::FP_ROUND, DL, MVT::f32, Src, Flags); in lowerFP_ROUND()
[all …]
H A DR600ISelLowering.cpp205 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
1728 case ISD::FP_ROUND: { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp211 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
2994 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
3035 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
3079 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
3522 case ISD::FP_ROUND: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2419 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2420 { ISD::FP_ROUND, MVT::v16f16, MVT::v16f32, { 1, 1, 1, 1 } }, // vcvtps2ph in getCastInstrCost()
2804 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, { 3, 1, 1, 1 } }, in getCastInstrCost()
2934 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, { 1, 1, 1, 1 } }, in getCastInstrCost()
3098 { ISD::FP_ROUND, MVT::f16, MVT::f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
3099 { ISD::FP_ROUND, MVT::v8f16, MVT::v8f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
3100 { ISD::FP_ROUND, MVT::v4f16, MVT::v4f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
3190 if ((ISD == ISD::FP_ROUND && SimpleDstTy == MVT::f16) || in getCastInstrCost()
H A DX86ISelDAGToDAG.cpp1167 case ISD::FP_ROUND: in PreprocessISelDAG()
1181 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1396 case ISD::FP_ROUND: in PreprocessISelDAG()
1427 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
H A DX86ISelLoweringCall.cpp1193 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, in LowerCallResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1886 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1906 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1907 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3145 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp911 setOperationAction(ISD::FP_ROUND, VT, Custom); in NVPTXTargetLowering()
918 setOperationAction(ISD::FP_ROUND, {MVT::v2bf16, MVT::v2f16}, Expand); in NVPTXTargetLowering()
2507 ISD::FP_ROUND, Loc, MVT::bf16, in LowerINT_TO_FP()
2927 case ISD::FP_ROUND: in LowerOperation()
5168 if (Op.getOpcode() == ISD::FP_ROUND) in combinePackingMovIntoStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp187 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
190 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
1594 : DAG.getNode(ISD::FP_ROUND, dl, ResTy, VecV, in resizeToWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1259 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1260 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1310 setOperationAction(ISD::FP_ROUND, VT, Custom); in PPCTargetLowering()
8989 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
9071 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
9469 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
12612 case ISD::FP_ROUND: in LowerOperation()
15560 DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, In.getOperand(0), in combineElementTruncationToVectorTruncation()
15605 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
15622 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND) in combineBVOfConsecutiveLoads()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1893 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()

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