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Searched refs:FP_EXTEND (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def57 DAG_INSTRUCTION(FPExt, 1, 0, experimental_constrained_fpext, FP_EXTEND)
H A DVPIntrinsics.def518 HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND, 0)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2658 : ISD::FP_EXTEND, in ExpandLegalINT_TO_FP()
3030 DAG.getNode(ISD::FP_EXTEND, DL, NewScalarVT, Node->getOperand(0)); in PromoteReduction()
3041 DAG.getNode(ISD::FP_EXTEND, DL, NewVecVT, Node->getOperand(j)); in PromoteReduction()
3305 case ISD::FP_EXTEND: { in ExpandNode()
3337 Op = DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Op); in ExpandNode()
3701 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4913 case ISD::FP_EXTEND: { in ConvertNodeToLibcall()
5306 ExtOp = ISD::FP_EXTEND; in PromoteNode()
5352 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
5373 if (ExtOp != ISD::FP_EXTEND) in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp116 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
587 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
871 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
1446 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1777 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
2417 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
2481 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2948 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
3405 case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break; in SoftPromoteHalfOperand()
H A DLegalizeVectorOps.cpp428 case ISD::FP_EXTEND: in LegalizeOp()
603 unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in PromoteSETCC()
696 case ISD::FP_EXTEND: in Promote()
724 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
H A DDAGCombiner.cpp1938 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
13212 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || in matchVSelectOpSizesWithSetCC()
15978 if (matcher.match(N0, ISD::FP_EXTEND)) { in visitFADDForFMACombine()
15985 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), in visitFADDForFMACombine()
15986 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), N1); in visitFADDForFMACombine()
15992 if (matcher.match(N1, ISD::FP_EXTEND)) { in visitFADDForFMACombine()
15999 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0)), in visitFADDForFMACombine()
16000 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0); in visitFADDForFMACombine()
16013 matcher.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
16014 matcher.getNode(ISD::FP_EXTEND, SL, VT, V), Z)); in visitFADDForFMACombine()
[all …]
H A DSelectionDAGDumper.cpp385 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
H A DLegalizeVectorTypes.cpp109 case ISD::FP_EXTEND: in ScalarizeVectorResult()
791 case ISD::FP_EXTEND: in ScalarizeVectorOperand()
894 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
995 SDValue Res = DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
1186 case ISD::FP_EXTEND: in SplitVectorResult()
3199 case ISD::FP_EXTEND: in SplitVectorOperand()
4496 case ISD::FP_EXTEND: in WidenVectorResult()
6409 case ISD::FP_EXTEND: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h916 FP_EXTEND, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp566 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
567 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
636 (ISD == ISD::FP_EXTEND && SrcTy.getScalarType() == MVT::f32 && in getCastInstrCost()
641 {ISD::FP_EXTEND, MVT::v2f32, 2}, in getCastInstrCost()
642 {ISD::FP_EXTEND, MVT::v4f32, 4}}; in getCastInstrCost()
828 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2750 { ISD::FP_EXTEND, MVT::nxv2f32, MVT::nxv2f16, 1}, in getCastInstrCost()
2751 { ISD::FP_EXTEND, MVT::nxv4f32, MVT::nxv4f16, 1}, in getCastInstrCost()
2752 { ISD::FP_EXTEND, MVT::nxv8f32, MVT::nxv8f16, 2}, in getCastInstrCost()
2755 { ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f16, 1}, in getCastInstrCost()
2756 { ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f16, 2}, in getCastInstrCost()
2757 { ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f16, 4}, in getCastInstrCost()
2760 { ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f32, 1}, in getCastInstrCost()
2761 { ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f32, 2}, in getCastInstrCost()
2762 { ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f32, 6}, in getCastInstrCost()
H A DAArch64ISelLowering.cpp558 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
852 setOperationAction(ISD::FP_EXTEND, V8Narrow, Expand); in AArch64TargetLowering()
1119 setTargetDAGCombine(ISD::FP_EXTEND); in AArch64TargetLowering()
1611 setOperationAction(ISD::FP_EXTEND, VT, Custom); in AArch64TargetLowering()
2064 setOperationAction(ISD::FP_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
3463 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
3464 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
3573 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
3574 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
4401 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h575 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
1280 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
1284 ISD::FP_EXTEND, 0),
1286 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
H A DX86ISelLoweringCall.cpp808 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
955 } else if (Copy->getOpcode() != ISD::FP_EXTEND) in isUsedByReturnOnly()
H A DX86TargetTransformInfo.cpp2297 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
2298 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, { 3, 1, 1, 1 } }, in getCastInstrCost()
2299 { ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32, { 4, 1, 1, 1 } }, // 2*vcvtps2pd+vextractf64x4 in getCastInstrCost()
2683 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 3, 1, 1, 1 } }, in getCastInstrCost()
2813 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp345 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand); in SITargetLowering()
548 setOperationAction({ISD::FP_EXTEND, ISD::STRICT_FP_EXTEND}, MVT::f32, Custom); in SITargetLowering()
549 setOperationAction({ISD::FP_EXTEND, ISD::STRICT_FP_EXTEND}, MVT::f64, Custom); in SITargetLowering()
736 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand); in SITargetLowering()
3776 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
5881 case ISD::FP_EXTEND: in LowerOperation()
6061 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in lowerFCMPIntrinsic()
6062 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in lowerFCMPIntrinsic()
6666 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) : in getFPExtOrFPRound()
10576 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in LowerFDIV16()
[all …]
H A DAMDGPUISelLowering.cpp2553 case ISD::FP_EXTEND: in valueIsKnownNeverF32Denorm()
2664 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in LowerFLOG2()
2706 X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X, Flags); in LowerFLOGCommon()
2844 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in lowerFEXP2()
2994 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, X, Flags); in lowerFEXP()
3633 SDValue PromotedSrc = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src); in LowerFP_TO_INT()
4885 case ISD::FP_EXTEND: in performFNegCombine()
H A DAMDGPUISelDAGToDAG.cpp668 case ISD::FP_EXTEND: in Select()
3474 if (Src.getOpcode() == ISD::FP_EXTEND) { in SelectVOP3PMadMixModsImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1080 case ISD::FP_EXTEND: in getCastInstrCost()
1087 : (ISD == ISD::FP_EXTEND) ? RISCV::VFWCVT_F_F_V in getCastInstrCost()
H A DRISCVISelLowering.cpp468 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom); in RISCVTargetLowering()
469 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in RISCVTargetLowering()
970 // RVV has native FP_ROUND & FP_EXTEND conversions where the element type in RISCVTargetLowering()
974 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1063 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1099 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1311 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
2922 Src = DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), MVT::f32, Src); in lowerFP_TO_INT_SAT()
6476 SDValue Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0)); in LowerOperation()
6491 case ISD::FP_EXTEND in LowerOperation()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp184 setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Custom); in initializeHVXLowering()
187 setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Legal); in initializeHVXLowering()
1577 return InpWidth < ResWidth ? DAG.getNode(ISD::FP_EXTEND, dl, ResTy, VecV) in resizeToWidth()
2242 assert(Op->getOpcode() == ISD::FP_EXTEND); in LowerHvxFpExtend()
3233 case ISD::FP_EXTEND: return LowerHvxFpExtend(Op, DAG); in LowerHvxOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1224 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1261 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in PPCTargetLowering()
1287 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
8223 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8226 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
8236 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8245 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8259 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8262 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
8269 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp786 setOperationAction(ISD::FP_EXTEND, VT, Custom); in NVPTXTargetLowering()
2661 DAG.getNode(ISD::FP_EXTEND, Loc, MVT::f32, Op.getOperand(0))); in LowerFP_TO_INT()
2720 Op = DAG.getNode(ISD::FP_EXTEND, Loc, F32, Narrow); in LowerFP_EXTEND()
2724 return DAG.getNode(ISD::FP_EXTEND, Loc, WideVT, Op); in LowerFP_EXTEND()
2796 case ISD::FP_EXTEND: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1900 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1928 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
3284 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp187 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
2000 case ISD::FP_EXTEND: in LowerConvertLow()

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