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Searched refs:FP_EXTEND (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp3190 {ISD::FP_EXTEND, MVT::f64, MVT::f32, 1}, // fcvt in getCastInstrCost()
3191 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2f32, 1}, // fcvtl in getCastInstrCost()
3192 {ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 2}, // fcvtl+fcvtl2 in getCastInstrCost()
3194 {ISD::FP_EXTEND, MVT::f32, MVT::f16, 1}, // fcvt in getCastInstrCost()
3195 {ISD::FP_EXTEND, MVT::f64, MVT::f16, 1}, // fcvt in getCastInstrCost()
3196 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, // fcvtl in getCastInstrCost()
3197 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, 2}, // fcvtl+fcvtl2 in getCastInstrCost()
3198 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2f16, 2}, // fcvtl+fcvtl in getCastInstrCost()
3199 {ISD::FP_EXTEND, MVT::v4f64, MVT::v4f16, 3}, // fcvtl+fcvtl2+fcvtl in getCastInstrCost()
3200 {ISD::FP_EXTEND, MVT::v8f64, MVT::v8f16, 6}, // 2 * fcvtl+fcvtl2+fcvtl in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp572 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
778 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal); in AArch64TargetLowering()
779 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Legal); in AArch64TargetLowering()
783 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in AArch64TargetLowering()
889 setOperationAction(ISD::FP_EXTEND, V8Narrow, Expand); in AArch64TargetLowering()
1162 setTargetDAGCombine(ISD::FP_EXTEND); in AArch64TargetLowering()
1705 setOperationAction(ISD::FP_EXTEND, VT, Custom); in AArch64TargetLowering()
1757 setOperationAction(ISD::FP_EXTEND, VT, Custom); in AArch64TargetLowering()
2300 setOperationAction(ISD::FP_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
3455 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitComparison()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def57 DAG_INSTRUCTION(FPExt, 1, 0, experimental_constrained_fpext, FP_EXTEND)
H A DVPIntrinsics.def490 HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2685 : ISD::FP_EXTEND, in ExpandLegalINT_TO_FP()
3067 DAG.getNode(ISD::FP_EXTEND, DL, NewVecVT, Node->getOperand(j)); in PromoteReduction()
3071 DAG.getNode(ISD::FP_EXTEND, DL, NewScalarVT, Node->getOperand(j)); in PromoteReduction()
3336 case ISD::FP_EXTEND: { in ExpandNode()
3368 Op = DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Op); in ExpandNode()
3840 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
5119 case ISD::FP_EXTEND: { in ConvertNodeToLibcall()
5517 ExtOp = ISD::FP_EXTEND; in PromoteNode()
5562 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
5583 if (ExtOp != ISD::FP_EXTEND) in PromoteNode()
[all …]
H A DLegalizeVectorOps.cpp442 case ISD::FP_EXTEND: in LegalizeOp()
630 unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in PromoteSETCC()
699 SDValue NewOp = DAG.getNode(ISD::FP_EXTEND, DL, NewOpVT, Node->getOperand(0)); in PromoteFloatVECREDUCE()
750 case ISD::FP_EXTEND: in Promote()
792 DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
H A DDAGCombiner.cpp1999 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
14072 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || in matchVSelectOpSizesWithSetCC()
16982 if (matcher.match(N0, ISD::FP_EXTEND)) { in visitFADDForFMACombine()
16989 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), in visitFADDForFMACombine()
16990 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), N1); in visitFADDForFMACombine()
16996 if (matcher.match(N1, ISD::FP_EXTEND)) { in visitFADDForFMACombine()
17003 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0)), in visitFADDForFMACombine()
17004 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0); in visitFADDForFMACombine()
17017 matcher.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
17018 matcher.getNode(ISD::FP_EXTEND, SL, VT, V), Z)); in visitFADDForFMACombine()
[all …]
H A DLegalizeFloatTypes.cpp122 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
632 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
1013 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
1603 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1996 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
2633 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
2710 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
3226 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
3748 case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break; in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp405 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
H A DLegalizeVectorTypes.cpp111 case ISD::FP_EXTEND: in ScalarizeVectorResult()
804 case ISD::FP_EXTEND: in ScalarizeVectorOperand()
942 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res) in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
1042 SDValue Res = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), in ScalarizeVecOp_FP_EXTEND()
1234 case ISD::FP_EXTEND: in SplitVectorResult()
3474 case ISD::FP_EXTEND: in SplitVectorOperand()
4865 case ISD::FP_EXTEND: in WidenVectorResult()
6856 case ISD::FP_EXTEND: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h960 FP_EXTEND, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp586 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
587 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
656 (ISD == ISD::FP_EXTEND && SrcTy.getScalarType() == MVT::f32 && in getCastInstrCost()
661 {ISD::FP_EXTEND, MVT::v2f32, 2}, in getCastInstrCost()
662 {ISD::FP_EXTEND, MVT::v4f32, 4}}; in getCastInstrCost()
848 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2414 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
2415 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, { 3, 1, 1, 1 } }, in getCastInstrCost()
2416 { ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32, { 4, 1, 1, 1 } }, // 2*vcvtps2pd+vextractf64x4 in getCastInstrCost()
2417 { ISD::FP_EXTEND, MVT::v16f32, MVT::v16f16, { 1, 1, 1, 1 } }, // vcvtph2ps in getCastInstrCost()
2418 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f16, { 2, 1, 1, 1 } }, // vcvtph2ps+vcvtps2pd in getCastInstrCost()
2803 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 3, 1, 1, 1 } }, in getCastInstrCost()
2933 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
3101 { ISD::FP_EXTEND, MVT::f32, MVT::f16, { 1, 1, 1, 1 } }, in getCastInstrCost()
3102 { ISD::FP_EXTEND, MVT::f64, MVT::f16, { 2, 1, 1, 1 } }, // vcvtph2ps+vcvtps2pd in getCastInstrCost()
3103 { ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, { 1, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86IntrinsicsInfo.h916 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
1621 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
1625 ISD::FP_EXTEND, 0),
1627 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
H A DX86ISelLoweringCall.cpp826 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
973 } else if (Copy->getOpcode() != ISD::FP_EXTEND) in isUsedByReturnOnly()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp186 setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Custom); in initializeHVXLowering()
189 setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Legal); in initializeHVXLowering()
1593 ? DAG.getNode(ISD::FP_EXTEND, dl, ResTy, VecV) in resizeToWidth()
2279 assert(Op->getOpcode() == ISD::FP_EXTEND); in LowerHvxFpExtend()
3270 case ISD::FP_EXTEND: return LowerHvxFpExtend(Op, DAG); in LowerHvxOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp352 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand); in SITargetLowering()
564 setOperationAction({ISD::FP_EXTEND, ISD::STRICT_FP_EXTEND}, MVT::f32, Custom); in SITargetLowering()
565 setOperationAction({ISD::FP_EXTEND, ISD::STRICT_FP_EXTEND}, MVT::f64, Custom); in SITargetLowering()
752 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand); in SITargetLowering()
3945 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
6228 case ISD::FP_EXTEND: in LowerOperation()
6405 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in lowerFCMPIntrinsic()
6406 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in lowerFCMPIntrinsic()
7017 ? DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) in getFPExtOrFPRound()
11252 SDValue LHSExt = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, LHS); in LowerFDIV16()
[all …]
H A DAMDGPUISelLowering.cpp2610 case ISD::FP_EXTEND: in valueIsKnownNeverF32Denorm()
2721 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in LowerFLOG2()
2763 X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X, Flags); in LowerFLOGCommon()
2901 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in lowerFEXP2()
3052 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, X, Flags); in lowerFEXP()
3697 SDValue PromotedSrc = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src); in LowerFP_TO_INT()
5119 case ISD::FP_EXTEND: in performFNegCombine()
H A DAMDGPUISelDAGToDAG.cpp784 case ISD::FP_EXTEND: in Select()
3663 if (Src.getOpcode() == ISD::FP_EXTEND) { in SelectVOP3PMadMixModsImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp910 setOperationAction(ISD::FP_EXTEND, VT, Custom); in NVPTXTargetLowering()
916 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand); in NVPTXTargetLowering()
2524 DAG.getNode(ISD::FP_EXTEND, Loc, MVT::f32, Op.getOperand(0))); in LowerFP_TO_INT()
2583 Op = DAG.getNode(ISD::FP_EXTEND, Loc, F32, Narrow); in LowerFP_EXTEND()
2587 return DAG.getNode(ISD::FP_EXTEND, Loc, WideVT, Op); in LowerFP_EXTEND()
2929 case ISD::FP_EXTEND: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1242 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1279 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in PPCTargetLowering()
1305 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
8289 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8292 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
8302 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8311 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8325 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8328 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
8335 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1885 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1905 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
3144 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1594 case ISD::FP_EXTEND: in getCastInstrCost()
1601 : (ISD == ISD::FP_EXTEND) ? RISCV::VFWCVT_F_F_V in getCastInstrCost()
H A DRISCVISelLowering.cpp1070 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1149 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1443 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
3084 Src = DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), MVT::f32, Src); in lowerFP_TO_INT_SAT()
3198 DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, SrcVal)); in lowerFP_TO_INT()
7446 SDValue Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0)); in LowerOperation()
7459 case ISD::FP_EXTEND: in LowerOperation()
7498 SDValue WidenVec = DAG.getNode(ISD::FP_EXTEND, DL, NVT, Op1); in LowerOperation()
7673 return DAG.getNode(ISD::FP_EXTEND, DL, VT, Res); in LowerOperation()
7736 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0)); in LowerOperation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp205 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
2390 case ISD::FP_EXTEND: in LowerConvertLow()

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