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Searched refs:FPU (Results 1 – 25 of 82) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR345.td103 multiclass SCR_FPU<ProcResourceKind FPU> {
105 def : WriteRes<WriteFAdd32, [FPU]> { let Latency = 3; }
106 def : WriteRes<WriteFAdd64, [FPU]> { let Latency = 3; }
107 def : WriteRes<WriteFMul32, [FPU]> { let Latency = 4; }
108 def : WriteRes<WriteFMul64, [FPU]> { let Latency = 4; }
109 def : WriteRes<WriteFMA32, [FPU]> { let Latency = 4; }
110 def : WriteRes<WriteFMA64, [FPU]> { let Latency = 4; }
111 def : WriteRes<WriteFSGNJ32, [FPU]> { let Latency = 2; }
112 def : WriteRes<WriteFSGNJ64, [FPU]> { let Latency = 2; }
113 def : WriteRes<WriteFMinMax32, [FPU]> { let Latency = 2; }
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/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DAArch64.cpp459 if (FPU & FPUMode) in getTargetDefines()
478 if (FPU & NeonMode) { in getTargetDefines()
484 if (FPU & SveMode) in getTargetDefines()
599 if ((FPU & NeonMode) && HasFullFP16) in getTargetDefines()
626 if ((FPU & SveMode) && HasBFloat16) { in getTargetDefines()
630 if ((FPU & SveMode) && HasMatmulFP64) in getTargetDefines()
633 if ((FPU & SveMode) && HasMatmulFP32) in getTargetDefines()
636 if ((FPU & SveMode) && HasMatMul) in getTargetDefines()
639 if ((FPU & NeonMode) && HasFP16FML) in getTargetDefines()
730 if (FPU & SveMode) in getTargetDefines()
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H A DARM.cpp508 FPU = 0; in handleTargetFeatures()
535 FPU |= VFP2FPU; in handleTargetFeatures()
541 FPU |= VFP3FPU; in handleTargetFeatures()
547 FPU |= VFP4FPU; in handleTargetFeatures()
553 FPU |= FPARMV8; in handleTargetFeatures()
558 FPU |= NeonFPU; in handleTargetFeatures()
593 FPU |= FPARMV8; in handleTargetFeatures()
639 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { in handleTargetFeatures()
658 .Case("neon", (FPU & NeonFPU) && !SoftFloat) in hasFeature()
659 .Case("vfp", FPU && !SoftFloat) in hasFeature()
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/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DLoongArch.cpp39 int FPU = -1; in getLoongArchABI() local
43 FPU = 64; in getLoongArchABI()
45 FPU = 32; in getLoongArchABI()
47 FPU = 0; in getLoongArchABI()
80 if (FPU != -1 && ImpliedFPU != FPU) in getLoongArchABI()
92 switch (FPU) { in getLoongArchABI()
185 StringRef FPU = A->getValue(); in getLoongArchTargetFeatures() local
186 if (FPU == "64") { in getLoongArchTargetFeatures()
189 } else if (FPU == "32") { in getLoongArchTargetFeatures()
193 } else if (FPU == "0" || FPU == "none") { in getLoongArchTargetFeatures()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td83 def : WriteRes<FPU, [Z196_FPUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
718 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
743 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
747 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
748 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
753 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
755 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
756 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
760 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
[all …]
H A DSystemZScheduleZEC12.td84 def : WriteRes<FPU, [ZEC12_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
756 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
781 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
785 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
786 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
791 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
793 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
794 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
798 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfoPOSIX_arm.cpp25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::FPU, fpscr) + \
29 sizeof(RegisterInfoPOSIX_arm::FPU))
32 sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
43 (sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
163 return sizeof(struct RegisterInfoPOSIX_arm::FPU); in GetFPRSize()
H A DRegisterContextDarwin_arm64.h80 struct FPU { struct
114 FPUWordCount = sizeof(FPU) / sizeof(uint32_t), // ARM_NEON_STATE64_COUNT
123 FPU fpu;
204 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
212 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextDarwin_x86_64.h80 struct FPU { struct
112 FPUWordCount = sizeof(FPU) / sizeof(uint32_t), argument
119 FPU fpu;
190 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
196 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextDarwin_arm.h98 struct FPU { struct
148 FPUWordCount = sizeof(FPU) / sizeof(uint32_t),
156 FPU fpu;
237 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) = 0;
245 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) = 0;
H A DRegisterContextMach_x86_64.cpp31 FPU &fpu) { in DoReadFPU()
50 const FPU &fpu) { in DoWriteFPU()
52 tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)), in DoWriteFPU()
H A DRegisterContextMach_arm.cpp31 int RegisterContextMach_arm::DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) { in DoReadFPU()
54 const FPU &fpu) { in DoWriteFPU()
56 tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)), in DoWriteFPU()
H A DRegisterContextDarwin_riscv32.h81 struct FPU { struct
141 FPUWordCount = sizeof(FPU) / sizeof(uint32_t),
149 FPU fpr;
233 virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpr) = 0;
241 virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpr) = 0;
H A DRegisterContextMach_x86_64.h25 int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override;
31 int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override;
H A DRegisterContextMach_arm.h24 int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override;
32 int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override;
H A DRegisterInfoPOSIX_arm64.cpp25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
49 sizeof(RegisterInfoPOSIX_arm64::FPU))
53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
308 return sizeof(struct RegisterInfoPOSIX_arm64::FPU); in GetFPRSize()
H A DRegisterContextPOSIX_arm.h54 size_t GetFPUSize() { return sizeof(RegisterInfoPOSIX_arm::FPU); } in GetFPUSize()
H A DRegisterContextDarwin_x86_64.cpp151 (LLVM_EXTENSION offsetof(RegisterContextDarwin_x86_64::FPU, reg) + \
156 sizeof(RegisterContextDarwin_x86_64::FPU))
166 #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg), \
170 sizeof(((RegisterContextDarwin_x86_64::FPU *) NULL)->reg[i].bytes), \
182 sizeof(RegisterContextDarwin_x86_64::FPU) + \
/freebsd/sys/contrib/openzfs/config/
H A Dkernel-fpu.m43 dnl # Handle differences in kernel FPU code.
12 dnl # 5.0: Wrappers have been introduced to save/restore the FPU state.
101 [kernel exports FPU functions])
113 [kernel exports FPU functions])
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68k.td42 "Is M68881 (FPU) ISA supported">;
46 "Is M68882 (FPU) ISA supported",
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMELFStreamer.cpp98 void emitFPU(ARM::FPUKind FPU) override;
256 void ARMTargetAsmStreamer::emitFPU(ARM::FPUKind FPU) { in emitFPU() argument
257 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
407 ARM::FPUKind FPU = ARM::FK_INVALID; member in __anonf150d5940111::ARMTargetELFStreamer
440 void emitFPU(ARM::FPUKind FPU) override;
930 void ARMTargetELFStreamer::emitFPU(ARM::FPUKind Value) { FPU = Value; } in emitFPU()
935 switch (FPU) { in emitFPUDefaultAttributes()
1046 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
1054 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
1084 FPU = ARM::FK_INVALID; in finishAttributeSection()
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp221 ARM::FPUKind ARM::parseFPU(StringRef FPU) { in parseFPU() argument
222 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
236 StringRef ARM::getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
237 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
250 .Default(FPU); in getFPUSynonym()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td49 // Mips 32-bit FPU Registers
52 // Mips 64-bit (aliased) FPU Registers
156 /// Mips Single point precision FPU Registers
164 /// Mips Double point precision FPU Registers (aliased
171 /// Mips Double point precision FPU Registers in MFP64 mode.
177 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
430 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
/freebsd/contrib/file/magic/Magdir/
H A Dolf63 >>36 lelong 1 MathCoPro/FPU/MAU Required
98 >>36 belong 1 MathCoPro/FPU/MAU Required
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td155 // Instructions of FPU pipeline

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