| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 328 …let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D1…
338 …let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D1…
346 let Defs = [VPR, FPSCR, FPSCR_NZCV];
347 …let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D1…
357 let Defs = [VPR, FPSCR, FPSCR_NZCV];
358 …let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D1…
1744 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1745 let Uses = [FPSCR] in {
2494 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
2501 // Application level FPSCR -> GPR
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| H A D | ARMRegisterInfo.td | 180 // We model fpscr with two registers: FPSCR models the control bits and will be
188 def FPSCR : ARMReg<3, "fpscr">;
190 let Aliases = [FPSCR];
414 // FPSCR, when the flags at the top of it are used as the input or
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| H A D | ARMBaseRegisterInfo.cpp | 208 markSuperRegs(Reserved, ARM::FPSCR); in getReservedRegs()
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| H A D | ARMISelLowering.cpp | 6413 SDValue FPSCR = in LowerGET_ROUNDING() local
6415 Chain = FPSCR.getValue(1); in LowerGET_ROUNDING()
6416 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerGET_ROUNDING()
6452 SDValue FPSCR = in LowerSET_ROUNDING() local
6454 Chain = FPSCR.getValue(1); in LowerSET_ROUNDING()
6455 FPSCR = FPSCR.getValue(0); in LowerSET_ROUNDING()
6459 FPSCR = DAG.getNode(ISD::AND, DL, MVT::i32, FPSCR, in LowerSET_ROUNDING()
6461 FPSCR = DAG.getNode(ISD::OR, DL, MVT::i32, FPSCR, RMValue); in LowerSET_ROUNDING()
6463 Chain, DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32), FPSCR}; in LowerSET_ROUNDING()
6477 SDValue FPSCR = in LowerSET_FPMODE() local
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| H A D | ARMScheduleSwift.td | 652 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
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| H A D | ARMInstrMVE.td | 5116 // Custom decoder method in order to add the FPSCR operand(s), which
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | README_P9.txt | 257 rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
262 rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
267 rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
272 rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
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| H A D | PPCInstrInfo.td | 182 // Extract FPSCR (not modeled at the DAG level).
2819 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2821 // When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsPowerPC.td | 37 // Get content from current FPSCR register
45 // Set FPSCR register, and return previous content
1602 // PowerPC set FPSCR Intrinsic Definitions.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 246 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR}, in initLLVMToCVRegMapping()
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