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Searched refs:FPRegs (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td86 def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
88 def FONES : VISInstD<0b001111111, "fones", FPRegs>;
90 def FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>;
92 def FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>;
94 def FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>;
96 def FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>;
98 def FORS : VISInst<0b001111101, "fors", FPRegs>;
100 def FNORS : VISInst<0b001100011, "fnors", FPRegs>;
102 def FANDS : VISInst<0b001110001, "fands", FPRegs>;
104 def FNANDS : VISInst<0b001101111, "fnands", FPRegs>;
[all …]
H A DSparcInstrInfo.td567 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
588 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
611 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
633 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;
637 defm LDFA : LoadASI<"ld", 0b110000, FPRegs>;
689 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
693 defm STFA : StoreASI<"st", 0b110100, FPRegs>;
1231 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1233 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1236 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
[all …]
H A DSparcInstr64Bit.td325 def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
326 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
383 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2, FPRegs:$f, RegCCOp:$rcond),
404 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
406 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
418 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
420 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
H A DSparcInstrAliases.td32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
55 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
638 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
643 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
H A DSparcRegisterInfo.td362 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
366 // The Low?FPRegs classes are used only for inline-asm constraints.
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp2104 SmallVector<CalleeSavedInfo, 18> FPRegs; in processFunctionBeforeFrameFinalized() local
2131 FPRegs.push_back(I); in processFunctionBeforeFrameFinalized()
2170 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized()
2171 int FI = FPRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwindCursor.hpp2430 double *FPRegs = reinterpret_cast<double *>( in stepWithTBTable() local
2434 32 - TBTable->tb.fpr_saved + i + unwPPCF0Index, FPRegs[i]); in stepWithTBTable()
2437 ptrToRegs = reinterpret_cast<char *>(FPRegs); in stepWithTBTable()