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Searched refs:FPRegs (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td58 def FPADD16S : VISInst<0b001010001, "fpadd16s", FPRegs>;
60 def FPADD32S : VISInst<0b001010011, "fpadd32s", FPRegs>;
62 def FPSUB16S : VISInst<0b001010101, "fpsub16s", FPRegs>;
64 def FPSUB32S : VISInst<0b001010111, "fpsub32s", FPRegs>;
70 (outs FPRegs:$rd), (ins DFPRegs:$rs2), "fpackfix $rs2, $rd">;
73 (outs DFPRegs:$rd), (ins FPRegs:$rs2), "fexpand $rs2, $rd">;
75 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
79 (outs DFPRegs:$rd), (ins FPRegs:$rs1, DFPRegs:$rs2),
82 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
85 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
[all …]
H A DSparcInstrInfo.td599 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
620 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
643 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
665 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;
669 defm LDFA : LoadASI<"ld", 0b110000, FPRegs>;
721 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
725 defm STFA : StoreASI<"st", 0b110100, FPRegs>;
1299 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1301 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1304 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
[all …]
H A DSparcInstrUAOSA.td48 def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
50 def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
53 def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
55 def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
H A DSparcInstr64Bit.td303 def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
304 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
361 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2, FPRegs:$f, RegCCOp:$rcond),
382 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
384 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
396 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
398 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
H A DSparcInstrAliases.td32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
55 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
705 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
710 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
H A DSparcRegisterInfo.td362 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
366 // The Low?FPRegs classes are used only for inline-asm constraints.
/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwindCursor.hpp2509 double *FPRegs = reinterpret_cast<double *>( in stepWithTBTable() local
2513 32 - TBTable->tb.fpr_saved + i + unwPPCF0Index, FPRegs[i]); in stepWithTBTable()
2516 ptrToRegs = reinterpret_cast<char *>(FPRegs); in stepWithTBTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp2107 SmallVector<CalleeSavedInfo, 18> FPRegs; in processFunctionBeforeFrameFinalized() local
2134 FPRegs.push_back(I); in processFunctionBeforeFrameFinalized()
2173 for (const CalleeSavedInfo &FPReg : FPRegs) { in processFunctionBeforeFrameFinalized()