| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaRegisterInfo.td | 256 class FPReg<bits<4> num, string n> : XtensaReg<n> {
260 def F0 : FPReg<0, "f0">, DwarfRegNum<[19]>;
261 def F1 : FPReg<1, "f1">, DwarfRegNum<[20]>;
262 def F2 : FPReg<2, "f2">, DwarfRegNum<[21]>;
263 def F3 : FPReg<3, "f3">, DwarfRegNum<[22]>;
264 def F4 : FPReg<4, "f4">, DwarfRegNum<[23]>;
265 def F5 : FPReg<5, "f5">, DwarfRegNum<[24]>;
266 def F6 : FPReg<6, "f6">, DwarfRegNum<[25]>;
267 def F7 : FPReg<7, "f7">, DwarfRegNum<[26]>;
268 def F8 : FPReg<8, "f8">, DwarfRegNum<[27]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 391 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; in replaceFPWithRealFP() local
396 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
408 MO.setReg(FPReg); in replaceFPWithRealFP()
654 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitPrologue() local
826 .addReg(FPReg) in emitPrologue()
1021 .addReg(FPReg, RegState::Kill) // Save FP. in emitPrologue()
1059 .addReg(FPReg) in emitPrologue()
1084 .addReg(FPReg) in emitPrologue()
1131 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); in emitPrologue()
1168 BuildMI(MBB, MBBI, dl, OrInst, FPReg) in emitPrologue()
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| H A D | PPCFastISel.cpp | 1113 Register FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned); in SelectIToFP() local
1114 if (!FPReg) in SelectIToFP()
1129 .addReg(FPReg); in SelectIToFP()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextWindows_x86_64.cpp | 72 } FPReg; typedef
75 (sizeof(GPR) + LLVM_EXTENSION offsetof(FPReg, regname))
79 #reg, NULL, sizeof(((FPReg *)nullptr)->reg), FPR_OFFSET(reg), \
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 88 Register FPReg = getFPReg(STI); in emitPrologue() local
151 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg) in emitPrologue()
157 nullptr, RI->getDwarfRegNum(FPReg, true))); in emitPrologue()
228 Register FPReg = getFPReg(STI); in emitEpilogue() local
263 .addReg(FPReg) in emitEpilogue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 1070 Register FPReg = RegInfo->getFrameRegister(MF); in spillCalleeSavedRegisters() local
1074 bool NeedsFrameRecordPush = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg); in spillCalleeSavedRegisters()
1082 if (NeedsFrameRecordPush && (Reg == FPReg.asMCReg() || Reg == ARM::LR)) in spillCalleeSavedRegisters()
1111 !MF.getRegInfo().isLiveIn(Reg) && !(hasFP(MF) && Reg == FPReg)) in spillCalleeSavedRegisters()
1160 Register FPReg = RegInfo->getFrameRegister(MF); in restoreCalleeSavedRegisters() local
1164 bool NeedsFrameRecordPop = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg); in restoreCalleeSavedRegisters()
1170 if (NeedsFrameRecordPop && (Reg == FPReg.asMCReg() || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
1185 if ((ARM::tGPRRegClass.contains(Reg)) && !(hasFP(MF) && Reg == FPReg)) in restoreCalleeSavedRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 726 MCRegister FPReg; // Frame pointer register member in __anonf150d5940111::ARMELFStreamer
1220 FPReg = ARM::SP; in EHReset()
1317 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); in FlushUnwindOpcodes()
1383 assert((NewSPReg == ARM::SP || NewSPReg == FPReg) && in emitSetFP()
1387 FPReg = NewFPReg; in emitSetFP()
1398 assert(FPReg == ARM::SP && "current FP must be SP"); in emitMovSP()
1402 FPReg = Reg; in emitMovSP()
1406 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); in emitMovSP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 636 MCRegister FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true); in generateCompactUnwindEncoding() local
639 FPReg = getXRegFromWReg(FPReg); in generateCompactUnwindEncoding()
641 if (LRReg != AArch64::LR || FPReg != AArch64::FP) in generateCompactUnwindEncoding()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1695 unsigned FPReg = getFPReg(Op); in handleSpecialFP() local
1701 FPKills |= 1U << FPReg; in handleSpecialFP()
1725 unsigned FPReg = getFPReg(Op); in handleSpecialFP() local
1729 Op.setReg(getSTReg(FPReg)); in handleSpecialFP()
1732 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
1749 unsigned FPReg = llvm::countr_zero(FPKills); in handleSpecialFP() local
1750 if (isLive(FPReg)) in handleSpecialFP()
1751 freeStackSlotAfter(Inst, FPReg); in handleSpecialFP()
1752 FPKills &= ~(1U << FPReg); in handleSpecialFP()
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| H A D | X86FrameLowering.cpp | 2905 Register FPReg = TRI->getFrameRegister(MF); in assignCalleeSavedSpillSlots() local
2907 if (TRI->regsOverlap(CSI[i].getReg(), FPReg)) { in assignCalleeSavedSpillSlots()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFrameLowering.cpp | 195 Register FPReg = LoongArch::R22; in emitPrologue() local
250 adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
256 MCCFIInstruction::cfiDefCfa(nullptr, RI->getDwarfRegNum(FPReg, true), in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 51 static constexpr MCPhysReg FPReg = RISCV::X8; variable
64 /*ra*/ RAReg, /*s0*/ FPReg, /*s1*/ RISCV::X9,
76 {/*fp*/ FPReg, -2},
385 case /*s0*/ FPReg: return 1; in getLibCallID()
1059 if (STI.isRegisterReservedByUser(FPReg)) in emitPrologue()
1063 assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved"); in emitPrologue()
1069 MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
1074 CFIBuilder.buildDefCFA(FPReg, RVFI->getVarArgsSaveSize()); in emitPrologue()
1272 RI->adjustReg(MBB, FirstScalarCSRRestoreInsn, DL, SPReg, FPReg, in emitEpilogue()
1436 if (FrameReg == FPReg) { in getFrameIndexReference()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 697 Register FPReg = MFI->getFrameOffsetReg(); in emitEntryFunctionPrologue() local
698 assert(FPReg != AMDGPU::FP_REG); in emitEntryFunctionPrologue()
699 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), FPReg).addImm(0); in emitEntryFunctionPrologue()
715 Register FPReg = MFI->getFrameOffsetReg(); in emitEntryFunctionPrologue() local
716 assert(FPReg != AMDGPU::FP_REG); in emitEntryFunctionPrologue()
725 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), FPReg) in emitEntryFunctionPrologue()
731 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32)).addImm(0).addReg(FPReg); in emitEntryFunctionPrologue()
732 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CMOVK_I32), FPReg).addImm(VGPRSize); in emitEntryFunctionPrologue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kFrameLowering.cpp | 817 Register FPReg = TRI->getFrameRegister(MF); in assignCalleeSavedSpillSlots() local
819 if (TRI->regsOverlap(CSI[i].getReg(), FPReg)) { in assignCalleeSavedSpillSlots()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 115 MCRegister FPReg; member in __anon6be9c9a00111::UnwindContext
118 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
134 void saveFPReg(MCRegister Reg) { FPReg = Reg; } in saveFPReg()
135 MCRegister getFPReg() const { return FPReg; } in getFPReg()
174 FPReg = ARM::SP; in reset()
12138 MCRegister FPReg = tryParseRegister(); in parseDirectiveSetFP() local
12140 if (check(!FPReg, FPRegLoc, "frame pointer register expected") || in parseDirectiveSetFP()
12153 UC.saveFPReg(FPReg); in parseDirectiveSetFP()
12177 getTargetStreamer().emitSetFP(FPReg, SPReg, Offset); in parseDirectiveSetFP()
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