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Searched refs:FPR128 (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoQ.td18 def QExt : ExtInfo<"", "", [HasStdExtQ], f128, FPR128, FPR32, FPR64, ?>;
28 def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
33 def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
148 def : InstAlias<"flq $rd, (${rs1})", (FLQ FPR128:$rd, GPR:$rs1, 0), 0>;
149 def : InstAlias<"fsq $rs2, (${rs1})", (FSQ FPR128:$rs2, GPR:$rs1, 0), 0>;
151 def : InstAlias<"fmv.q $rd, $rs", (FSGNJ_Q FPR128:$rd, FPR128:$rs,
152 FPR128:$rs)>;
153 def : InstAlias<"fabs.q $rd, $rs", (FSGNJX_Q FPR128:$rd, FPR128:$rs,
154 FPR128:$rs)>;
155 def : InstAlias<"fneg.q $rd, $rs", (FSGNJN_Q FPR128:$rd, FPR128:$rs,
[all …]
H A DRISCVInstrInfoZfa.td180 def FLI_Q : FPFLI_r<0b1111011, 0b00001, 0b000, FPR128, "fli.q">,
184 def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
185 def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
188 def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">,
190 def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128,
195 def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
196 def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
202 def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b00001, 0b000, GPR, FPR128, "fmvh.x.q">;
203 def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
234 (FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
[all …]
H A DRISCVRegisterInfo.td477 def FPR128 : RISCVRegisterClass<[f128], 128, (add
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td3733 // Match all load 128 bits width whose type is compatible with FPR128
3852 // Match all load 128 bits width whose type is compatible with FPR128
4046 // Match all load 128 bits width whose type is compatible with FPR128
4441 def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)),
4442 (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s16:$offset)>;
4465 def : Pat<(store (f128 FPR128:$Rt),
4468 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;
4469 def : Pat<(store (f128 FPR128:$Rt),
4472 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
4522 // Match all store 128 bits width whose type is compatible with FPR128
[all …]
H A DAArch64RegisterInfo.td528 def FPR128 : RegisterClass<"AArch64",
540 128, (trunc FPR128, 16)> {
549 128, (trunc FPR128, 8)> {
575 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
577 [(rotl FPR128, 0), (rotl FPR128, 1),
578 (rotl FPR128, 2)]>;
580 [(rotl FPR128, 0), (rotl FPR128, 1),
581 (rotl FPR128, 2), (rotl FPR128, 3)]>;
611 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
760 defm VecListOne : VectorList<1, FPR64, FPR128>;
[all …]
H A DAArch64FrameLowering.cpp3186 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enumerator
3279 RPI.Type = RegPairInfo::FPR128; in computeCalleeSaveRegisterPairs()
3320 case RegPairInfo::FPR128: in computeCalleeSaveRegisterPairs()
3399 RPI.Type != RegPairInfo::FPR128 && !RPI.isPaired() && in computeCalleeSaveRegisterPairs()
3525 case RegPairInfo::FPR128: in spillCalleeSavedRegisters()
3755 case RegPairInfo::FPR128: in restoreCalleeSavedRegisters()
H A DAArch64InstrFormats.td12022 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
12023 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
12024 [(set (v4i32 FPR128:$dst),
12025 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
12036 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
12037 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
12038 [(set (v4i32 FPR128:$dst),
12039 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
12118 : CryptoRRR<op0, op1, (outs FPR128:$Vdst), (ins FPR128:$Vd, FPR128:$Vn, V128:$Vm),
H A DAArch64SMEInstrInfo.td288 …defm _FPR128 : CoalescerBarrierPseudo<FPR128, [f128, v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f…
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp315 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; in isQForm() local
317 return Op.isReg() && FPR128.contains(Op.getReg()); in isQForm()
322 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; in isFpOrNEON() local
332 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td228 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
250 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td203 def FPR128 : RegisterClass<"CSKY",