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Searched refs:FP64 (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
37 def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
43 def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>;
45 def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64, 4>;
51 def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64, GR32>;
55 def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64, GR64>;
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H A DSystemZInstrDFP.td23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
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H A DSystemZInstrFP.td22 def SelectF64 : SelectWrapper<f64, FP64>;
30 defm CondStoreF64 : CondStores<FP64, simple_store,
40 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;
46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
59 def LTDBR : UnaryRRE<"ltdbr", 0xB312, null_frag, FP64, FP64>;
68 def LTDBRCompare_Pseudo : Pseudo<(outs), (ins FP64:$R1), []>;
72 defm : CompareZeroFP<LTDBRCompare_Pseudo, FP64>;
77 def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
78 def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
83 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>;
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H A DSystemZRegisterInfo.td244 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
H A DSystemZInstrVector.td1805 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>;
1811 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1812 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1814 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1815 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DMips.cpp143 case FP64: in getTargetDefines()
148 if (FPMode == FP64 || IsSingleFloat) in getTargetDefines()
221 .Case("fp64", FPMode == FP64) in hasFeature()
259 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat && in validateTarget()
265 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" || in validateTarget()
271 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" || in validateTarget()
H A DMips.h59 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; enumerator
90 return FP64; in getDefaultFPMode()
353 FPMode = FP64; in handleTargetFeatures()
389 FPMode = FP64; in handleTargetFeatures()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.td31 def FP64 : WebAssemblyReg<"%FP64">;
64 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
H A DWebAssemblyRegisterInfo.cpp48 WebAssembly::FP64}) in getReservedRegs()
148 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
H A DWebAssemblyFrameLowering.cpp189 ? WebAssembly::FP64 in getOpcConst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h119 bool FP64) const;
122 bool FP64) const;
H A DMipsSEFrameLowering.cpp85 MachineBasicBlock::iterator I, bool FP64) const;
87 MachineBasicBlock::iterator I, bool FP64) const;
288 bool FP64) const { in expandBuildPairF64()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
344 bool FP64) const { in expandExtractElementF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
H A DMipsSEInstrInfo.cpp754 bool FP64) const { in expandExtractElementF64()
786 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) in expandExtractElementF64()
787 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), in expandExtractElementF64()
796 bool isMicroMips, bool FP64) const { in expandBuildPairF64()
842 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) in expandBuildPairF64()
843 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), in expandBuildPairF64()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUFeatures.td10 "FP64",
H A DR600Subtarget.h39 bool FP64 = false; variable
H A DGCNSubtarget.h101 bool FP64 = false; variable
363 return FP64; in hasFP64()
371 return FP64; in hasHWFP64()
H A DSIRegisterInfo.td1120 int FP64 = 4;
1213 def VSrc_f64 : SrcRegOrImm9 <VS_64, "OPW64", "OPERAND_REG_IMM_FP64", 64, OperandSemantics.FP64> {
1309 …c_64_f64 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_FP64", 64, OperandSemantics.FP64>;
1316 …56_f64 : SrcRegOrImm9 <VReg_256, "OPW256", "OPERAND_REG_INLINE_C_FP64", 64, OperandSemantics.FP64>;
1360 …64_f64 : SrcRegOrImmA9 <AReg_64, "OPW64", "OPERAND_REG_INLINE_AC_FP64", 64, OperandSemantics.FP64>;
1363 …_f64 : SrcRegOrImmA9 <AReg_256, "OPW256", "OPERAND_REG_INLINE_AC_FP64", 64, OperandSemantics.FP64>;
H A DSIDefines.h279 FP64 = 4, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp438 AMDGPU::OperandSemantics::FP64)); in decodeOperand_VSrc_f64()
1569 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); in decodeNonVGPRSrcOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td171 "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
H A DAArch64InstrInfo.td6057 // Round FP64 to BF16.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2706 // SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions
/freebsd/share/misc/
H A Dpci_vendors15409 1148 5841 FDDI SK-5841 (SK-NET FDDI-FP64)