| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 985 FP16_TO_FP, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 420 case ISD::FP16_TO_FP: return "fp16_to_fp"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 125 case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break; in SoftenFloatResult()
2573 return ISD::FP16_TO_FP; in GetPromotionOpcode()
2810 case ISD::FP16_TO_FP: in PromoteFloatResult()
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| H A D | LegalizeDAG.cpp | 921 DAG.getNode(SVT == MVT::f16 ? ISD::FP16_TO_FP : ISD::BF16_TO_FP, in LegalizeLoadOps()
3832 case ISD::FP16_TO_FP: in ExpandNode()
3838 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0)); in ExpandNode()
4976 case ISD::FP16_TO_FP: in ConvertNodeToLibcall()
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| H A D | DAGCombiner.cpp | 2037 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N); in visit()
18930 case ISD::FP16_TO_FP: in eliminateFPCastPair()
18978 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
18979 TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal) in visitFP_EXTEND()
18980 return DAG.getNode(ISD::FP16_TO_FP, DL, VT, N0.getOperand(0)); in visitFP_EXTEND()
27766 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
27775 assert((Op == ISD::FP16_TO_FP || Op == ISD::BF16_TO_FP) && in visitFP16_TO_FP()
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| H A D | SelectionDAG.cpp | 6329 case ISD::FP16_TO_FP: in getNode()
6861 case ISD::FP16_TO_FP: in FoldConstantArithmetic()
6864 APFloat FPV(Opcode == ISD::FP16_TO_FP ? APFloat::IEEEhalf() in FoldConstantArithmetic()
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| H A D | LegalizeIntegerTypes.cpp | 2014 case ISD::FP16_TO_FP: in PromoteIntegerOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 470 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in AMDGPUTargetLowering()
2612 case ISD::FP16_TO_FP: in valueIsKnownNeverF32Denorm()
3713 (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) { in LowerFP_TO_INT()
5161 case ISD::FP16_TO_FP: { in performFNegCombine()
5173 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
5250 case ISD::FP16_TO_FP: { in performFAbsCombine()
5259 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
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| H A D | SIISelLowering.cpp | 587 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote); in SITargetLowering()
588 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32); in SITargetLowering()
13398 case ISD::FP16_TO_FP: in isCanonicalized()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1690 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in SparcTargetLowering()
1692 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in SparcTargetLowering()
1694 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 121 ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1882 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in HexagonTargetLowering()
1883 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 474 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in MipsTargetLowering()
476 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 207 setOperationAction(ISD::FP16_TO_FP, MVT::f32, in LoongArchTargetLowering()
254 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in LoongArchTargetLowering()
518 case ISD::FP16_TO_FP: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 220 setOperationAction(ISD::FP16_TO_FP, FPVT, Expand); in initSPUActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 599 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 150 setOperationAction(ISD::FP16_TO_FP, T, Expand); in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 244 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); in PPCTargetLowering()
246 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in PPCTargetLowering()
249 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 573 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom); in RISCVTargetLowering()
631 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in RISCVTargetLowering()
7698 case ISD::FP16_TO_FP: { in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1440 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in ARMTargetLowering()
1446 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 440 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16, in X86TargetLowering()
2692 ISD::FP16_TO_FP, in X86TargetLowering()
33631 case ISD::FP16_TO_FP: in LowerOperation()
60669 case ISD::FP16_TO_FP: return combineFP16_TO_FP(N, DAG, Subtarget); in PerformDAGCombine()
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