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Searched refs:FP16 (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFP.td40 def LZER_16 : InherentRRE<"lzer", 0xB374, FP16, fpimm0>;
53 def LER16 : UnaryRR<"ler", 0x38, null_frag, FP16, FP16>;
54 def LDR16 : UnaryRR<"ldr", 0x28, null_frag, FP16, FP16>;
87 // fcopysign with an FP16 result.
89 def CPSDRhh : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP16>;
90 def CPSDRhs : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP32>;
91 def CPSDRhd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP64>;
96 def : Pat<(fcopysign FP16:$src1, (f128 FP128:$src2)),
97 (CPSDRhd FP16:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
99 def : Pat<(fcopysign FP16:$src1, (f128 VR128:$src2)),
[all …]
H A DSystemZRegisterInfo.td259 defm FP16 : SystemZRegClass<"FP16", [f16], 16, (sequence "F%uH", 0, 15),
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_fp16.td1 //===--- arm_fp16.td - ARM FP16 compiler interface ------------------------===//
9 // This file defines the TableGen definitions from which the ARM FP16 header
16 // ARMv8.2-A FP16 intrinsics.
H A Driscv_andes_vector.td96 // Andes Vector Packed FP16 Extension (XAndesVPackFPH)
H A Darm_neon.td1664 // ARMv8.2-A FP16 vector intrinsics for A32/A64.
1667 // ARMv8.2-A FP16 one-operand vector intrinsics.
1705 // ARMv8.2-A FP16 two-operands vector intrinsics.
1759 // ARMv8.2-A FP16 three-operands vector intrinsics.
1765 // ARMv8.2-A FP16 lane vector intrinsics.
1786 // ARMv8.2-A FP16 vector intrinsics for A64 only.
1810 // ARMv8.2-A FP16 lane vector intrinsics.
1849 // ARMv8.2-A FP16 reduction vector intrinsics.
1881 // v8.2-A FP16 fused multiply-add long instructions.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXAndes.td22 // Andes Vector Packed FP16 Extension
H A DIntrinsicsX86.td4983 // VNNI FP16
5475 // AMX-FP16 - Intel FP16 AMX extensions
H A DIntrinsicsNVVM.td360 // FP16 ops are identified by accumulator & result type.
H A DIntrinsicsAArch64.td541 // v8.2-A FP16 Fused Multiply-Add Long
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FMV.td55 def : FMVExtension<"fp16", "FP16">;
H A DAArch64Features.td210 "Enable FP16 FML instructions", [FeatureFullFP16, FeatureNEON]>;
562 "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions", [FeatureSVE]>;
H A DSMEInstrFormats.td2846 // SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers
3053 // FMLAL (multiple and indexed vector, FP8 to FP16)
3112 // FMLAL (single and indexed vector, FP8 to FP16)
H A DAArch64InstrInfo.td1739 // ARMv8.2-A FP16 Fused Multiply-Add Long
1869 // inside the multiclass as the FP16 versions need different predicates.
5362 // Pattern for FP16 and BF16 immediates
8400 // Patterns for FP16 Intrinsics - requires reg copy to/from as i16s not supported.
H A DAArch64InstrFormats.td6562 // FCVTN (FP16 to FP8)
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssembly.td50 "Enable FP16 instructions">;
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DARM.cpp1103 namespace FP16 { namespace
1164 {&NEON::FP16::BuiltinStrings, NEON::FP16::BuiltinInfos, in getTargetBuiltins()
H A DAArch64.cpp57 namespace FP16 { namespace
742 {&NEON::FP16::BuiltinStrings, NEON::FP16::BuiltinInfos, in getTargetBuiltins()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrFormats.td1682 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2062 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2092 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2120 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2151 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
H A DARMISelDAGToDAG.cpp125 bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16);
985 bool FP16) { in IsAddressingMode5() argument
1005 const int Scale = FP16 ? 2 : 4; in IsAddressingMode5()
1021 if (FP16) in IsAddressingMode5()
1033 if (FP16) in IsAddressingMode5()
H A DARMFeatures.td37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
/freebsd/contrib/llvm-project/clang/include/clang/CIR/Dialect/IR/
H A DCIRTypes.td110 def CIR_FP16 : CIR_FloatType<"FP16", "f16"> {
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1631 "Andes Vector Packed FP16 Extension", [FeatureStdExtF]>;
1635 "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)">;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td199 //AMX-FP16
H A DX86InstrAVX10.td15 // VNNI FP16
H A DX86InstrSSE.td4037 // Always select FP16 instructions if available.

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