Home
last modified time | relevance | path

Searched refs:FP16 (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_fp16.td1 //===--- arm_fp16.td - ARM FP16 compiler interface ------------------------===//
9 // This file defines the TableGen definitions from which the ARM FP16 header
16 // ARMv8.2-A FP16 intrinsics.
H A Darm_neon.td1656 // ARMv8.2-A FP16 vector intrinsics for A32/A64.
1659 // ARMv8.2-A FP16 one-operand vector intrinsics.
1697 // ARMv8.2-A FP16 two-operands vector intrinsics.
1750 // ARMv8.2-A FP16 three-operands vector intrinsics.
1756 // ARMv8.2-A FP16 lane vector intrinsics.
1777 // ARMv8.2-A FP16 vector intrinsics for A64 only.
1801 // ARMv8.2-A FP16 lane vector intrinsics.
1852 // ARMv8.2-A FP16 reduction vector intrinsics.
1886 // v8.2-A FP16 fused multiply-add long instructions.
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td1117 int FP16 = 1;
1136 def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>;
1171 def VSrc_f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>;
1205 …f16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>;
1211 def VSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_V2FP16", 16, OperandSemantics.FP16>;
1225 …: SrcRegOrImmDeferred9<VS_32, "OPW16", "OPERAND_REG_IMM_FP16_DEFERRED", 16, OperandSemantics.FP16>;
1231 …egOrImmDeferred9<VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_FP16_DEFERRED", 16, OperandSemantics.FP16>;
1295 … VCSrc_f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_FP16", 16, OperandSemantics.FP16>;
1300 …rc_v2f16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_V2FP16", 16, OperandSemantics.FP16>;
1307 …c_64_f16 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_FP16", 16, OperandSemantics.FP16>;
[all …]
H A DSIDefines.h276 FP16 = 1, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td199 //AMX-FP16
H A DX86.td169 // FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be
171 // FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
H A DX86InstrSSE.td4037 // Always select FP16 instructions if available.
H A DX86InstrAVX512.td11557 // Always select FP16 instructions if available.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrFormats.td1687 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2067 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2097 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2125 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2156 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
H A DARMISelDAGToDAG.cpp134 bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16);
994 bool FP16) { in IsAddressingMode5() argument
1014 const int Scale = FP16 ? 2 : 4; in IsAddressingMode5()
1030 if (FP16) in IsAddressingMode5()
1042 if (FP16) in IsAddressingMode5()
H A DARMFeatures.td37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td210 "Enable FP16 FML instructions", [FeatureFullFP16]>;
H A DSMEInstrFormats.td2513 // SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers
2719 // FMLAL (multiple and indexed vector, FP8 to FP16)
H A DAArch64InstrInfo.td1436 // ARMv8.2-A FP16 Fused Multiply-Add Long
1566 // inside the multiclass as the FP16 versions need different predicates.
4896 // Pattern for FP16 and BF16 immediates
7877 // Patterns for FP16 Intrinsics - requires reg copy to/from as i16s not supported.
H A DAArch64InstrFormats.td6205 // FCVTN (FP16 to FP8)
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1710 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); in decodeSDWASrc16()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsX86.td5262 // AMX-FP16 - Intel FP16 AMX extensions
H A DIntrinsicsAArch64.td552 // v8.2-A FP16 Fused Multiply-Add Long
H A DIntrinsicsNVVM.td221 // FP16 ops are identified by accumulator & result type.
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1166 // Loads FP16 constant into a register.