| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 90 DAG_FUNCTION(minnum, 2, 0, experimental_constrained_minnum, FMINNUM)
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| H A D | VPIntrinsics.def | 406 VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1006 FMINNUM, enumerator
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| H A D | BasicTTIImpl.h | 2025 ISD = ISD::FMINNUM; in getTypeBasedIntrinsicInstrCost()
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| H A D | TargetLowering.h | 2904 case ISD::FMINNUM: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | GenericOpcodes.td | 797 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
803 // The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
820 // differs from FMINNUM/FMAXNUM in the handling of signaling NaNs, and
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 196 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 394 case ISD::FMINNUM: in LegalizeOp()
1008 case ISD::FMINNUM: in Expand()
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| H A D | LegalizeFloatTypes.cpp | 74 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
1404 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
2631 case ISD::FMINNUM: in PromoteFloatResult()
3073 case ISD::FMINNUM: in SoftPromoteHalfResult()
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| H A D | TargetLowering.cpp | 8397 assert((Opcode == ISD::FMINNUM || Opcode == ISD::FMAXNUM || in createSelectForFMINNUM_FMAXNUM()
8402 ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in createSelectForFMINNUM_FMAXNUM()
8420 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ? in expandFMINNUM_FMAXNUM()
8458 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM; in expandFMINNUM_FMAXNUM()
8485 unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM; in expandFMINIMUM_FMAXIMUM()
11178 bool MinMaxLegal = isOperationLegal(ISD::FMINNUM, SrcVT) && in expandFP_TO_INT_SAT()
11186 Clamped = DAG.getNode(ISD::FMINNUM, dl, SrcVT, Clamped, MaxFloatNode); in expandFP_TO_INT_SAT()
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| H A D | SelectionDAGBuilder.cpp | 3747 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
3749 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) || in visitSelect()
3751 TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()))) in visitSelect()
3752 Opc = ISD::FMINNUM; in visitSelect()
6863 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, in visitIntrinsicCall()
9251 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| H A D | LegalizeDAG.cpp | 3632 case ISD::FMINNUM: in ExpandNode()
4498 case ISD::FMINNUM: in ConvertNodeToLibcall()
5434 case ISD::FMINNUM: in PromoteNode()
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| H A D | SelectionDAG.cpp | 471 return ISD::FMINNUM; in getVecReduceBaseOpcode()
5460 case ISD::FMINNUM: in isKnownNeverNaN()
6793 case ISD::FMINNUM: in foldConstantFPMath()
11931 case ISD::FMINNUM: in isNeutralConstant()
13176 case ISD::FMINNUM: in getNeutralElement()
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| H A D | LegalizeVectorTypes.cpp | 147 case ISD::FMINNUM: in ScalarizeVectorResult()
1247 case ISD::FMINNUM: in SplitVectorResult()
4381 case ISD::FMINNUM: in WidenVectorResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 210 ISD::FREM, ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM, in SITargetLowering()
519 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, {MVT::f32, MVT::f64}, in SITargetLowering()
752 setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, MVT::f16, Custom); in SITargetLowering()
759 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, in SITargetLowering()
804 setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, {MVT::v2f16, MVT::v4f16}, in SITargetLowering()
899 ISD::FMINNUM, in SITargetLowering()
5832 case ISD::FMINNUM: in LowerOperation()
8467 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
12688 case ISD::FMINNUM: in isCanonicalized()
13032 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
[all …]
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| H A D | AMDGPUISelLowering.cpp | 395 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, in AMDGPUTargetLowering()
530 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, in AMDGPUTargetLowering()
652 case ISD::FMINNUM: in fnegFoldsIntoOpcode()
4704 return ISD::FMINNUM; in inverseMinMax()
4705 case ISD::FMINNUM: in inverseMinMax()
4835 case ISD::FMINNUM: in performFNegCombine()
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| H A D | AMDGPUISelDAGToDAG.cpp | 166 case ISD::FMINNUM: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1506 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP, in HexagonTargetLowering()
1658 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, ISD::FLDEXP, in HexagonTargetLowering()
1790 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in HexagonTargetLowering()
1839 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 130 setOperationAction(ISD::FMINNUM, T, Legal); in initializeHVXLowering()
167 setOperationAction(ISD::FMINNUM, P, Custom); in initializeHVXLowering()
3169 case ISD::FMINNUM: in LowerHvxOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 713 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 628 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SystemZTargetLowering()
633 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
638 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in SystemZTargetLowering()
643 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
648 setOperationAction(ISD::FMINNUM, MVT::f128, Legal); in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 430 ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT, in RISCVTargetLowering()
454 ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in RISCVTargetLowering()
947 ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB, in RISCVTargetLowering()
982 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, VT, Legal); in RISCVTargetLowering()
1370 ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM, in RISCVTargetLowering()
1477 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); in RISCVTargetLowering()
6073 case ISD::FMINNUM: in getRISCVVLOp()
7020 case ISD::FMINNUM: in LowerOperation()
13069 case ISD::FMINNUM: in combineBinOpToReduce()
16840 case ISD::FMINNUM in PerformDAGCombine()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 365 setOperationAction(ISD::FMINNUM, VT, Legal); in addMVEVectorTypes()
797 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); in ARMTargetLowering()
1517 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in ARMTargetLowering()
1520 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1522 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1533 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in ARMTargetLowering()
1571 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1573 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal); in ARMTargetLowering()
4217 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
10306 case ISD::VECREDUCE_FMIN: BaseOpcode = ISD::FMINNUM; break; in LowerVecReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 367 setOperationAction(ISD::FMINNUM, MVT::f32, Expand); in MipsTargetLowering()
371 setOperationAction(ISD::FMINNUM, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 259 setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, VT, Legal); in initSPUActions()
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