| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 374 X86_INTRINSIC_DATA(avx_min_pd_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
375 X86_INTRINSIC_DATA(avx_min_ps_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
914 X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN,
916 X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN,
1433 X86_INTRINSIC_DATA(avx512fp16_min_ph_128, INTR_TYPE_2OP, X86ISD::FMIN, 0),
1434 X86_INTRINSIC_DATA(avx512fp16_min_ph_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
1435 X86_INTRINSIC_DATA(avx512fp16_min_ph_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN,
1512 X86_INTRINSIC_DATA(sse_min_ps, INTR_TYPE_2OP, X86ISD::FMIN, 0),
1543 X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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| H A D | X86ISelLowering.h | 265 FMIN, enumerator
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| H A D | X86InstrFragmentsSIMD.td | 38 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 // Commutative and Associative FMIN and FMAX.
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| H A D | X86ISelLowering.cpp | 21361 X86ISD::FMIN, dl, SrcVT, MaxFloatNode, MinClamped); in LowerFP_TO_INT_SAT()
28292 MinMaxOp = X86ISD::FMIN; in LowerFMINIMUM_FMAXIMUM()
32673 case X86ISD::FMIN: in ReplaceNodeResults()
33726 NODE_NAME_CASE(FMIN) in getTargetNodeName()
34156 case X86ISD::FMIN: in isBinOp()
42525 case X86ISD::FMIN: in SimplifyDemandedVectorEltsForTargetNode()
44961 case X86ISD::FMIN: in scalarizeExtEltFP()
45959 Opcode = X86ISD::FMIN; in combineSelect()
45967 Opcode = X86ISD::FMIN; in combineSelect()
45977 Opcode = X86ISD::FMIN; in combineSelect()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA57.td | 483 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
487 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
489 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
491 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
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| H A D | AArch64SchedOryon.td | 1560 "^(FMAX|FMIN)(V|NMV)v",
1568 "^(FMAX|FMIN)(NMP|P)v",
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| H A D | AArch64SchedNeoverseN2.td | 1105 def : InstRW<[N2Write_4cyc_1V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
1108 def : InstRW<[N2Write_6cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
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| H A D | AArch64SchedNeoverseV2.td | 1608 def : InstRW<[V2Write_4cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
1611 def : InstRW<[V2Write_6cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
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| H A D | AArch64InstrInfo.td | 5000 defm FMIN : TwoOperandFPData<0b0101, "fmin", any_fminimum>;
5531 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", any_fminimum>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 133 FMAX, FMIN, enumerator
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| H A D | RISCVInstrInfoF.td | 54 def riscv_fmin : SDNode<"RISCVISD::FMIN", SDTFPBinOp>;
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| H A D | RISCVInstrInfoVVLPatterns.td | 597 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in
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| H A D | RISCVISelLowering.cpp | 5889 Op.getOpcode() == ISD::FMAXIMUM ? RISCVISD::FMAX : RISCVISD::FMIN; in lowerFMAXIMUM_FMINIMUM()
20422 NODE_NAME_CASE(FMIN) in getTargetNodeName()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_sve.td | 2129 // == SMIN / UMIN / FMIN ==
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 1181 defm FMIN : F3<"min", fminnum>;
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