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Searched refs:FMAXNUM (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp95 case ISD::FMAXNUM: in hasNativeBF16Support()
H A DNVPTXISelLowering.cpp544 case ISD::FMAXNUM: in NVPTXTargetLowering()
977 for (const auto &Op : {ISD::FMINNUM, ISD::FMAXNUM}) { in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3878 { ISD::FMAXNUM, MVT::f32, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3879 { ISD::FMAXNUM, MVT::v4f32, { 1, 1, 3, 3 } }, in getIntrinsicInstrCost()
3880 { ISD::FMAXNUM, MVT::v8f32, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3881 { ISD::FMAXNUM, MVT::v16f32, { 4, 4, 3, 3 } }, in getIntrinsicInstrCost()
3882 { ISD::FMAXNUM, MVT::f64, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3883 { ISD::FMAXNUM, MVT::v2f64, { 1, 1, 3, 3 } }, in getIntrinsicInstrCost()
3884 { ISD::FMAXNUM, MVT::v4f64, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3885 { ISD::FMAXNUM, MVT::v8f64, { 3, 3, 3, 3 } }, in getIntrinsicInstrCost()
4039 { ISD::FMAXNUM, MVT::f32, { 2, 7, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS in getIntrinsicInstrCost()
4040 { ISD::FMAXNUM, MVT::v4f32, { 2, 7, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def90 DAG_FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
H A DVPIntrinsics.def386 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1060 FMAXNUM, enumerator
H A DBasicTTIImpl.h2316 ISD = ISD::FMAXNUM; in getTypeBasedIntrinsicInstrCost()
H A DTargetLowering.h2989 case ISD::FMAXNUM: in isCommutativeBinOp()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp208 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
H A DLegalizeFloatTypes.cpp76 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1559 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
2869 case ISD::FMAXNUM: in PromoteFloatResult()
3355 case ISD::FMAXNUM: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp406 case ISD::FMAXNUM: in LegalizeOp()
1136 case ISD::FMAXNUM: in Expand()
H A DSelectionDAG.cpp480 return ISD::FMAXNUM; in getVecReduceBaseOpcode()
5799 case ISD::FMAXNUM: in isKnownNeverNaN()
7249 case ISD::FMAXNUM: in foldConstantFPMath()
12511 case ISD::FMAXNUM: { in isNeutralConstant()
12520 if (Opcode == ISD::FMAXNUM) in isNeutralConstant()
13796 case ISD::FMAXNUM: { in getNeutralElement()
13802 if (Opcode == ISD::FMAXNUM) in getNeutralElement()
H A DSelectionDAGBuilder.cpp3814 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
3816 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) || in visitSelect()
3818 TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()))) in visitSelect()
3819 Opc = ISD::FMAXNUM; in visitSelect()
6889 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, in visitIntrinsicCall()
9400 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
H A DLegalizeDAG.cpp3756 case ISD::FMAXNUM: { in ExpandNode()
4670 case ISD::FMAXNUM: in ConvertNodeToLibcall()
5645 case ISD::FMAXNUM: in PromoteNode()
H A DTargetLowering.cpp8623 assert((Opcode == ISD::FMINNUM || Opcode == ISD::FMAXNUM || in createSelectForFMINNUM_FMAXNUM()
8718 unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM; in expandFMINIMUM_FMAXIMUM()
8813 unsigned IEEE2008Op = Opc == ISD::FMINIMUMNUM ? ISD::FMINNUM : ISD::FMAXNUM; in expandFMINIMUMNUM_FMAXIMUMNUM()
11687 isOperationLegal(ISD::FMAXNUM, SrcVT); in expandFP_TO_INT_SAT()
11692 Clamped = DAG.getNode(ISD::FMAXNUM, dl, SrcVT, Clamped, MinFloatNode); in expandFP_TO_INT_SAT()
H A DLegalizeVectorTypes.cpp155 case ISD::FMAXNUM: in ScalarizeVectorResult()
1306 case ISD::FMAXNUM: in SplitVectorResult()
4750 case ISD::FMAXNUM: in WidenVectorResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp397 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, MVT::f32, Legal); in AMDGPUTargetLowering()
543 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, in AMDGPUTargetLowering()
666 case ISD::FMAXNUM: in fnegFoldsIntoOpcode()
4931 case ISD::FMAXNUM: in inverseMinMax()
4934 return ISD::FMAXNUM; in inverseMinMax()
5066 case ISD::FMAXNUM: in performFNegCombine()
H A DSIISelLowering.cpp217 ISD::FREM, ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM, in SITargetLowering()
535 {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM}, in SITargetLowering()
776 {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM}, in SITargetLowering()
785 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, in SITargetLowering()
832 {ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM}, in SITargetLowering()
958 ISD::FMAXNUM, in SITargetLowering()
6174 case ISD::FMAXNUM: in LowerOperation()
9064 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
13453 case ISD::FMAXNUM: in isCanonicalized()
13795 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td846 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
869 // differs from FMINNUM/FMAXNUM in the handling of signaling NaNs, and
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp793 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp371 setOperationAction(ISD::FMAXNUM, VT, Legal); in addMVEVectorTypes()
783 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in ARMTargetLowering()
1476 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
1479 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1481 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1493 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
1552 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1554 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); in ARMTargetLowering()
4287 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
10354 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp685 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering()
690 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
695 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering()
700 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
705 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp453 ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, in RISCVTargetLowering()
475 ISD::FMINNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM, in RISCVTargetLowering()
1007 ISD::FMAXNUM, in RISCVTargetLowering()
1080 {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM, ISD::FMINIMUMNUM}, VT, in RISCVTargetLowering()
1510 ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM, in RISCVTargetLowering()
1632 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM, ISD::FMUL}); in RISCVTargetLowering()
7083 case ISD::FMAXNUM: in getRISCVVLOp()
8138 case ISD::FMAXNUM: in LowerOperation()
14953 case ISD::FMAXNUM: in combineBinOpToReduce()
19879 case ISD::FMAXNUM: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp369 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in MipsTargetLowering()
373 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in MipsTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp805 ISD::FMAXNUM, in AArch64TargetLowering()
904 ISD::FROUNDEVEN, ISD::FMINNUM, ISD::FMAXNUM, in AArch64TargetLowering()
1245 ISD::FMAXNUM, ISD::FMINIMUM, ISD::FMAXIMUM, in AArch64TargetLowering()
1688 setOperationAction(ISD::FMAXNUM, VT, Custom); in AArch64TargetLowering()
1772 setOperationAction(ISD::FMAXNUM, VT, Custom); in AArch64TargetLowering()
1791 for (auto Opcode : {ISD::FADD, ISD::FMA, ISD::FMAXIMUM, ISD::FMAXNUM, in AArch64TargetLowering()
2082 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM, in addTypeForNEON()
2294 setOperationAction(ISD::FMAXNUM, VT, Default); in addTypeForFixedLengthSVE()
7474 case ISD::FMAXNUM: in LowerOperation()
22117 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()

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