| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 515 FMAD, enumerator
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| H A D | TargetLowering.h | 3381 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 664 case ISD::FMAD: in fnegFoldsIntoOpcode()
933 case ISD::FMAD: { in getNegatedExpression()
2035 : (unsigned)ISD::FMAD; in LowerDIVREM24()
2121 unsigned FMAD = in LowerUDIVREM64() local
2124 ? (unsigned)ISD::FMAD in LowerUDIVREM64()
2129 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
2138 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
5037 case ISD::FMAD: { in performFNegCombine()
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| H A D | AMDGPUCodeGenPrepare.cpp | 1294 auto FMAD = !ST.hasMadMacF32Insts() in expandDivRem24Impl() local
1297 Value *FR = Builder.CreateIntrinsic(FMAD, in expandDivRem24Impl()
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| H A D | SIISelLowering.cpp | 497 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
632 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
1046 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
11250 isOperationLegal(ISD::FMAD, MVT::f32) ? ISD::FMAD : ISD::FMA; in LowerFDIV16()
13392 case ISD::FMAD: in isCanonicalized()
14407 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
14408 return ISD::FMAD; in getFusedOpcode()
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| H A D | R600ISelLowering.cpp | 164 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
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| H A D | AMDGPUISelDAGToDAG.cpp | 184 case ISD::FMAD: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 312 case ISD::FMAD: return "fmad"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 2880 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
3364 case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break; in SoftPromoteHalfResult()
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| H A D | DAGCombiner.cpp | 1984 case ISD::FMAD: return visitFMAD(N); in visit()
16908 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
16912 return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); in visitFADDForFMACombine()
17140 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
17290 return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); in visitFSUBForFMACombine()
17459 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
18227 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FMAD, DL, VT, {N0, N1, N2})) in visitFMAD()
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| H A D | SelectionDAG.cpp | 5744 case ISD::FMAD: { in isKnownNeverNaN()
7957 case ISD::FMAD: { in getNode()
7968 if (Opcode == ISD::FMAD) { in getNode()
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| H A D | LegalizeDAG.cpp | 3829 case ISD::FMAD: in ExpandNode()
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| H A D | TargetLowering.cpp | 7655 case ISD::FMAD: { in getNegatedExpression()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 366 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 2266 if (auto FMAD = in instCombineSVEVectorFAdd() local
2270 return FMAD; in instCombineSVEVectorFAdd()
2286 if (auto FMAD = in instCombineSVEVectorFAddU() local
2290 return FMAD; in instCombineSVEVectorFAddU()
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| H A D | AArch64SchedA510.td | 1090 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_(ZPmZZ|ZPZZZ)_[HSD]")>;
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| H A D | AArch64SchedA320.td | 1112 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_(ZPmZZ|ZPZZZ)_[HSD]")>;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 797 ISD::FMAD, ISD::SMIN, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 533 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46786 case ISD::FMAD: in scalarizeExtEltFP()
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