| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 501 FMAD, enumerator
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| H A D | TargetLowering.h | 3280 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 651 case ISD::FMAD: in fnegFoldsIntoOpcode()
914 case ISD::FMAD: { in getNegatedExpression()
1978 : (unsigned)ISD::FMAD; in LowerDIVREM24()
2064 unsigned FMAD = in LowerUDIVREM64() local
2067 ? (unsigned)ISD::FMAD in LowerUDIVREM64()
2072 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
2081 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
4805 case ISD::FMAD: { in performFNegCombine()
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| H A D | AMDGPUCodeGenPrepare.cpp | 1276 auto FMAD = !ST->hasMadMacF32Insts() in expandDivRem24Impl() local
1279 Value *FR = Builder.CreateIntrinsic(FMAD, in expandDivRem24Impl()
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| H A D | R600ISelLowering.cpp | 160 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
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| H A D | SIISelLowering.cpp | 482 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
616 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
980 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
12628 case ISD::FMAD: in isCanonicalized()
13594 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
13595 return ISD::FMAD; in getFusedOpcode()
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| H A D | AMDGPUISelDAGToDAG.cpp | 188 case ISD::FMAD: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 295 case ISD::FMAD: return "fmad"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 2640 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
3080 case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break; in SoftPromoteHalfResult()
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| H A D | DAGCombiner.cpp | 1925 case ISD::FMAD: return visitFMAD(N); in visit()
15904 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
15908 return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); in visitFADDForFMACombine()
16136 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
16291 return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); in visitFSUBForFMACombine()
16461 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
17227 return DAG.getNode(ISD::FMAD, DL, VT, N0, N1, N2); in visitFMAD()
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| H A D | SelectionDAG.cpp | 5408 case ISD::FMAD: { in isKnownNeverNaN()
7425 case ISD::FMAD: { in getNode()
7436 if (Opcode == ISD::FMAD) { in getNode()
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| H A D | LegalizeDAG.cpp | 3690 case ISD::FMAD: in ExpandNode()
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| H A D | TargetLowering.cpp | 7436 case ISD::FMAD: { in getNegatedExpression()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 1602 if (auto FMAD = in instCombineSVEVectorFAdd() local
1606 return FMAD; in instCombineSVEVectorFAdd()
1622 if (auto FMAD = in instCombineSVEVectorFAddU() local
1626 return FMAD; in instCombineSVEVectorFAddU()
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| H A D | AArch64SchedA510.td | 1090 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_(ZPmZZ|ZPZZZ)_[HSD]")>;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 393 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 716 ISD::FMAD, ISD::SMIN, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 507 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44947 case ISD::FMAD: in scalarizeExtEltFP()
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