| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 97 DAG_FUNCTION(ldexp, 2, 1, experimental_constrained_ldexp, FLDEXP)
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1018 FLDEXP, enumerator
|
| H A D | BasicTTIImpl.h | 2304 ISD = ISD::FLDEXP; in getTypeBasedIntrinsicInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 328 case ISD::FLDEXP: return "fldexp"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 131 case ISD::FLDEXP: in SoftenFloatResult()
1608 case ISD::FLDEXP: in ExpandFloatResult()
2883 case ISD::FLDEXP: R = PromoteFloatRes_ExpOp(N); break; in PromoteFloatResult()
3367 case ISD::FLDEXP: R = SoftPromoteHalfRes_ExpOp(N); break; in SoftPromoteHalfResult()
|
| H A D | LegalizeVectorTypes.cpp | 162 case ISD::FLDEXP: in ScalarizeVectorResult()
1136 case ISD::FLDEXP: in SplitVectorResult()
3485 case ISD::FLDEXP: in SplitVectorOperand()
4852 case ISD::FLDEXP: in WidenVectorResult()
6835 case ISD::FLDEXP: in WidenVectorOperand()
|
| H A D | LegalizeDAG.cpp | 2218 bool IsSignedArgument = Node->getOpcode() == ISD::FLDEXP; in ExpandFPLibCall()
3788 case ISD::FLDEXP: in ExpandNode()
4844 case ISD::FLDEXP: in ConvertNodeToLibcall()
5728 case ISD::FLDEXP: in PromoteNode()
|
| H A D | LegalizeVectorOps.cpp | 425 case ISD::FLDEXP: in LegalizeOp()
|
| H A D | SelectionDAGBuilder.cpp | 6925 setValue(&I, DAG.getNode(ISD::FLDEXP, sdl, in visitIntrinsicCall()
9541 if (visitBinaryFloatCall(I, ISD::FLDEXP)) in visitCall()
|
| H A D | LegalizeIntegerTypes.cpp | 2049 case ISD::FLDEXP: in PromoteIntegerOperand()
|
| H A D | SelectionDAG.cpp | 5765 case ISD::FLDEXP: { in isKnownNeverNaN()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 220 ISD::FLDEXP, ISD::FFREXP, ISD::FLOG, ISD::FLOG2, in SITargetLowering()
552 setOperationAction({ISD::FLDEXP, ISD::STRICT_FLDEXP}, {MVT::f32, MVT::f64}, in SITargetLowering()
625 setOperationAction({ISD::FLDEXP, ISD::STRICT_FLDEXP}, MVT::f16, Custom); in SITargetLowering()
6182 case ISD::FLDEXP: in LowerOperation()
7187 return DAG.getNode(ISD::FLDEXP, DL, VT, Op.getOperand(0), TruncExp); in lowerFLDEXP()
11794 SDValue SqrtX = DAG.getNode(ISD::FLDEXP, DL, MVT::f64, X, ScaleUp, Flags); in lowerFSQRTF64()
11825 SqrtRet = DAG.getNode(ISD::FLDEXP, DL, MVT::f64, SqrtRet, ScaleDown, Flags); in lowerFSQRTF64()
13402 case ISD::FLDEXP: in isCanonicalized()
15423 return DAG.getNode(ISD::FLDEXP, SL, VT, LHS, SelectNode, N->getFlags()); in performFMulCombine()
15762 case ISD::FLDEXP: in PerformDAGCombine()
|
| H A D | AMDGPUISelLowering.cpp | 3140 SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); in lowerFEXP()
3370 return DAG.getNode(ISD::FLDEXP, SL, MVT::f32, FVal, ShAmt); in LowerINT_TO_FP32()
3403 SDValue LdExp = DAG.getNode(ISD::FLDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
6163 case ISD::FLDEXP: in isKnownNeverNaNForTargetNode()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 164 case ISD::FLDEXP: in fp16SrcZerosHighBits()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 859 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 569 def fldexp : SDNode<"ISD::FLDEXP" , SDTFPExpOp>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1728 ISD::FSINCOS, ISD::FLDEXP, in HexagonTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1971 setOperationAction(ISD::FLDEXP, MVT::f64, Custom); in AArch64TargetLowering()
1972 setOperationAction(ISD::FLDEXP, MVT::f32, Custom); in AArch64TargetLowering()
1973 setOperationAction(ISD::FLDEXP, MVT::f16, Custom); in AArch64TargetLowering()
1974 setOperationAction(ISD::FLDEXP, MVT::bf16, Custom); in AArch64TargetLowering()
1985 for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP}) in AArch64TargetLowering()
1992 for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP}) in AArch64TargetLowering()
7558 case ISD::FLDEXP: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1579 for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP}) in ARMTargetLowering()
1586 for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP}) in ARMTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 877 setOperationAction(ISD::FLDEXP, VT, Expand); in PPCTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 539 ISD::FLOG10, ISD::FLDEXP, ISD::FFREXP}, in RISCVTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 640 setOperationAction(ISD::FLDEXP, VT, Action); in X86TargetLowering()
2631 for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP}) in X86TargetLowering()
|