| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1032 FEXP10, enumerator
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| H A D | BasicTTIImpl.h | 2292 ISD = ISD::FEXP10; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 263 case ISD::FEXP10: return "fexp10"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 105 case ISD::FEXP10: R = SoftenFloatRes_FEXP10(N); break; in SoftenFloatResult()
1586 case ISD::FEXP10: ExpandFloatRes_FEXP10(N, Lo, Hi); break; in ExpandFloatResult()
2841 case ISD::FEXP10: in PromoteFloatResult()
3326 case ISD::FEXP10: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 433 case ISD::FEXP10: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 102 case ISD::FEXP10: in ScalarizeVectorResult()
1223 case ISD::FEXP10: in SplitVectorResult()
4908 case ISD::FEXP10: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4792 case ISD::FEXP10: in ConvertNodeToLibcall()
5815 case ISD::FEXP10: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 6839 case Intrinsic::exp10: Opcode = ISD::FEXP10; break; in visitIntrinsicCall()
9535 if (visitUnaryFloatCall(I, ISD::FEXP10)) in visitCall()
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| H A D | SelectionDAG.cpp | 5753 case ISD::FEXP10: in isKnownNeverNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 405 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
425 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
546 ISD::FEXP10, ISD::FLOG2, ISD::FREM, in AMDGPUTargetLowering()
1453 case ISD::FEXP10: in LowerOperation()
1499 case ISD::FEXP10: in ReplaceNodeResults()
3038 const bool IsExp10 = Op.getOpcode() == ISD::FEXP10; in lowerFEXP()
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| H A D | SIISelLowering.cpp | 221 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 812 ISD::FEXP2, ISD::FEXP10, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 566 def fexp10 : SDNode<"ISD::FEXP10" , SDTFPUnaryOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 396 setOperationAction(ISD::FEXP10, VT, Expand); in addMVEVectorTypes()
879 setOperationAction(ISD::FEXP10, MVT::v2f64, Expand); in ARMTargetLowering()
902 setOperationAction(ISD::FEXP10, MVT::v4f32, Expand); in ARMTargetLowering()
921 setOperationAction(ISD::FEXP10, MVT::v2f32, Expand); in ARMTargetLowering()
1070 setOperationAction(ISD::FEXP10, MVT::f64, Expand); in ARMTargetLowering()
1509 setOperationAction(ISD::FEXP10, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 755 ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in AArch64TargetLowering()
1243 ISD::FEXP10, ISD::FRINT, ISD::FROUND, in AArch64TargetLowering()
1733 setOperationAction(ISD::FEXP10, VT, Expand); in AArch64TargetLowering()
2024 setOperationAction(ISD::FEXP10, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 538 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in RISCVTargetLowering()
775 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, ISD::FLOG10}; in RISCVTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 628 setOperationAction(ISD::FEXP10, VT, Action); in X86TargetLowering()
961 setOperationAction(ISD::FEXP10, MVT::f80, Expand); in X86TargetLowering()
982 setOperationAction(ISD::FEXP10, VT, Expand); in X86TargetLowering()
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