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Searched refs:FCVT_W_RV64 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h117 FCVT_W_RV64, enumerator
H A DRISCVInstrInfoF.td46 : SDNode<"RISCVISD::FCVT_W_RV64", SDT_RISCVFCVT_W_RV64>;
H A DRISCVISelLowering.cpp2929 Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64; in lowerFP_TO_INT_SAT()
12234 unsigned Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64; in ReplaceNodeResults()
12275 DAG.getNode(RISCVISD::FCVT_W_RV64, DL, MVT::i64, Op0, in ReplaceNodeResults()
15373 Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64; in performFP_TO_INTCombine()
15426 Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64; in performFP_TO_INT_SATCombine()
17986 case RISCVISD::FCVT_W_RV64: in ComputeNumSignBitsForTargetNode()
20413 NODE_NAME_CASE(FCVT_W_RV64) in getTargetNodeName()