| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 152 #define FCOS 10 macro
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| H A D | lex.c | 56 { "cos", FCOS, BLTIN },
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| H A D | run.c | 2098 case FCOS: in bltin()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 76 DAG_FUNCTION(cos, 1, 1, experimental_constrained_cos, FCOS)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 963 FCOS, enumerator
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| H A D | BasicTTIImpl.h | 1977 ISD = ISD::FCOS; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
408 case ISD::FCOS: in LowerOperation()
698 case ISD::FCOS: in LowerTrig()
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| H A D | SIISelLowering.cpp | 212 ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, in SITargetLowering()
540 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
599 setOperationAction({ISD::FP_ROUND, ISD::STRICT_FP_ROUND, ISD::FCOS, in SITargetLowering()
5773 case ISD::FCOS: in LowerOperation()
11168 case ISD::FCOS: in LowerTrig()
12684 case ISD::FCOS: in isCanonicalized()
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| H A D | AMDGPUISelDAGToDAG.cpp | 151 case ISD::FCOS: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 212 case ISD::FCOS: return "fcos"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 90 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; in SoftenFloatResult()
1420 case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break; in ExpandFloatResult()
2603 case ISD::FCOS: in PromoteFloatResult()
3044 case ISD::FCOS: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2330 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3645 case ISD::FCOS: { in ExpandNode()
3654 if (Node->getOpcode() == ISD::FCOS) in ExpandNode()
4530 case ISD::FCOS: in ConvertNodeToLibcall()
5542 case ISD::FCOS: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 403 case ISD::FCOS: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 96 case ISD::FCOS: in ScalarizeVectorResult()
1171 case ISD::FCOS: in SplitVectorResult()
4534 case ISD::FCOS: in WidenVectorResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 928 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 659 def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1801 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1806 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1811 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 120 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1655 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 400 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
405 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
414 setOperationAction(ISD::FCOS , MVT::f64, Custom); in PPCTargetLowering()
420 setOperationAction(ISD::FCOS , MVT::f32, Custom); in PPCTargetLowering()
862 setOperationAction(ISD::FCOS, VT, Expand); in PPCTargetLowering()
1191 setOperationAction(ISD::FCOS, MVT::f128, Expand); in PPCTargetLowering()
11798 case ISD::FCOS: return lowerCos(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 450 setOperationAction(ISD::FCOS, MVT::f32, Expand); in MipsTargetLowering()
451 setOperationAction(ISD::FCOS, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 378 setOperationAction(ISD::FCOS, VT, Expand); in addMVEVectorTypes()
881 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
904 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); in ARMTargetLowering()
922 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
1065 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1460 setOperationAction(ISD::FCOS, MVT::f32, Expand); in ARMTargetLowering()
1461 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1543 setOperationAction(ISD::FCOS, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 132 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 179 setOperationAction(ISD::FCOS, MVT::f32, Expand); in LoongArchTargetLowering()
216 setOperationAction(ISD::FCOS, MVT::f64, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 250 setOperationAction(ISD::FCOS, VT, Expand); in initSPUActions()
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