| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.h | 66 FCOPYSIGN, enumerator
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| H A D | NVPTXISelLowering.cpp | 942 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in NVPTXTargetLowering()
943 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand); in NVPTXTargetLowering()
944 setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand); in NVPTXTargetLowering()
945 setOperationAction(ISD::FCOPYSIGN, MVT::v2bf16, Expand); in NVPTXTargetLowering()
946 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in NVPTXTargetLowering()
947 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in NVPTXTargetLowering()
1093 MAKE_CASE(NVPTXISD::FCOPYSIGN) in getTargetNodeName()
2384 return DAG.getNode(NVPTXISD::FCOPYSIGN, DL, VT, In1, In2); in LowerFCOPYSIGN()
2469 RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A); in LowerFROUND64()
2919 case ISD::FCOPYSIGN: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 521 FCOPYSIGN, enumerator
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| H A D | BasicTTIImpl.h | 2331 ISD = ISD::FCOPYSIGN; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 94 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; in SoftenFloatResult()
1171 case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break; in SoftenFloatOperand()
1445 return DAG.getNode(ISD::FCOPYSIGN, dl, LVT, LHS, RHS); in SoftenFloatOp_FCOPYSIGN()
1575 case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break; in ExpandFloatResult()
2292 case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break; in ExpandFloatOperand()
2391 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), in ExpandFloatOp_FCOPYSIGN()
2622 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break; in PromoteFloatOperand()
2828 case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break; in PromoteFloatResult()
3311 case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break; in SoftPromoteHalfResult()
3739 case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break; in SoftPromoteHalfOperand()
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| H A D | SelectionDAGDumper.cpp | 315 case ISD::FCOPYSIGN: return "fcopysign"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 413 case ISD::FCOPYSIGN: in LegalizeOp()
1032 case ISD::FCOPYSIGN: in Expand()
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| H A D | LegalizeDAG.cpp | 1780 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) { in ExpandFABS()
1782 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero); in ExpandFABS()
3719 case ISD::FCOPYSIGN: in ExpandNode()
5727 case ISD::FCOPYSIGN: in PromoteNode()
5739 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN); in PromoteNode()
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| H A D | LegalizeVectorTypes.cpp | 151 case ISD::FCOPYSIGN: in ScalarizeVectorResult()
1137 case ISD::FCOPYSIGN: SplitVecRes_FPOp_MultiType(N, Lo, Hi); break; in SplitVectorResult()
3424 case ISD::FCOPYSIGN: Res = SplitVecOp_FPOpDifferentTypes(N); break; in SplitVectorOperand()
4843 case ISD::FCOPYSIGN: in WidenVectorResult()
6836 case ISD::FCOPYSIGN: in WidenVectorOperand()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | TargetOpcodes.def | 713 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does
715 /// floating point. X and the result must have the same type. FCOPYSIGN(f32,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 372 VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1814 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1815 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1816 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 121 ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 495 setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Custom); in RISCVTargetLowering()
519 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in RISCVTargetLowering()
1094 setOperationAction(ISD::FCOPYSIGN, VT, Legal); in RISCVTargetLowering()
1184 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in RISCVTargetLowering()
1467 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in RISCVTargetLowering()
1509 ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FSQRT, in RISCVTargetLowering()
1649 {ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER, in RISCVTargetLowering()
6892 assert(Op.getOpcode() == ISD::FCOPYSIGN && "Unexpected opcode"); in lowerFCOPYSIGN()
7023 VP_CASE(FCOPYSIGN) // VP_FCOPYSIGN in getRISCVVLOp()
8186 case ISD::FCOPYSIGN: in LowerOperation()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 237 setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Legal); in SITargetLowering()
501 setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand); in SITargetLowering()
769 setOperationAction(ISD::FCOPYSIGN, in SITargetLowering()
991 ISD::FCOPYSIGN}); in SITargetLowering()
6208 case ISD::FCOPYSIGN: in LowerOperation()
7298 return DAG.getNode(ISD::FCOPYSIGN, SL, MagVT, Mag, SignAsHalf16); in lowerFCOPYSIGN()
11983 DAG.getNode(ISD::FCOPYSIGN, DL, MVT::f32, MagHi, SignOpElt); in performFCopySignCombine()
12029 return DAG.getNode(ISD::FCOPYSIGN, DL, N->getValueType(0), N->getOperand(0), in performFCopySignCombine()
13430 case ISD::FCOPYSIGN: in isCanonicalized()
15777 case ISD::FCOPYSIGN: in PerformDAGCombine()
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| H A D | AMDGPUISelLowering.cpp | 552 ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, ISD::SETCC, in AMDGPUTargetLowering()
1647 if (Val.getOpcode() == ISD::FCOPYSIGN) in peekFPSignOps()
2516 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFROUNDEVEN()
2578 SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X); in LowerFROUND()
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| H A D | R600ISelLowering.cpp | 168 setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in MipsTargetLowering()
357 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in MipsTargetLowering()
1343 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 223 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 865 setOperationAction({ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 551 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
739 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in AArch64TargetLowering()
740 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in AArch64TargetLowering()
742 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in AArch64TargetLowering()
743 setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Custom); in AArch64TargetLowering()
745 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); in AArch64TargetLowering()
746 setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Promote); in AArch64TargetLowering()
863 setOperationAction(ISD::FCOPYSIGN, V4Narrow, Custom); in AArch64TargetLowering()
873 setOperationAction(ISD::FCOPYSIGN, V8Narrow, Custom); in AArch64TargetLowering()
1684 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in AArch64TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 556 for (auto Op : {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN}) in SystemZTargetLowering()
741 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SystemZTargetLowering()
795 ISD::FCOPYSIGN, in SystemZTargetLowering()
8553 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, ValOp, WideOp); in combineFCOPYSIGN()
9148 case ISD::FCOPYSIGN: return combineFCOPYSIGN(N, DCI); in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 460 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
461 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
463 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
464 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
1156 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
1157 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal); in PPCTargetLowering()
1302 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 607 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
667 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
687 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in X86TargetLowering()
748 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in X86TargetLowering()
749 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in X86TargetLowering()
770 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
825 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); in X86TargetLowering()
906 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom); in X86TargetLowering()
975 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
1067 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom); in X86TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 249 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initSPUActions()
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