Home
last modified time | relevance | path

Searched refs:FADD (Results 1 – 25 of 65) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def52 DAG_INSTRUCTION(FAdd, 2, 1, experimental_constrained_fadd, FADD)
108 // constrained FMA or FMUL + FADD intrinsics.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp953 { ISD::FADD, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
954 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
968 { ISD::FADD, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
969 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1099 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd in getArithmeticInstrCost()
1157 { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd in getArithmeticInstrCost()
1158 { ISD::FADD, MVT::f32, { 1, 4, 1, 1 } }, // vaddss in getArithmeticInstrCost()
1159 { ISD::FADD, MVT::v2f64, { 1, 4, 1, 1 } }, // vaddpd in getArithmeticInstrCost()
1160 { ISD::FADD, MVT::v4f32, { 1, 4, 1, 1 } }, // vaddps in getArithmeticInstrCost()
1161 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 2 } }, // vaddpd in getArithmeticInstrCost()
[all …]
H A DX86IntrinsicsInfo.h447 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD,
449 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD,
1170 X86_INTRINSIC_DATA(avx512fp16_add_ph_512, INTR_TYPE_2OP, ISD::FADD,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td15 CheckOpcode<[FADD,
H A DP9InstrResources.td416 (instregex "FADD(S)?$"),
476 (instregex "FADD(S)?_rec$"),
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def112 ADD_BINARY_VVP_OP_COMPACT(FADD) REGISTER_PACKED(VVP_FADD)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h397 FADD, enumerator
H A DSDPatternMatch.h626 return BinaryOpc_match<LHS, RHS, true>(ISD::FADD, L, R);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp5420 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5423 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5436 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5439 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5442 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5457 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5460 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5463 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5466 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
5469 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2()
[all …]
H A DLegalizeVectorOps.cpp354 case ISD::FADD: in LegalizeOp()
1666 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT()
1687 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()
H A DSelectionDAGBuilder.h549 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
H A DDAGCombiner.cpp1920 case ISD::FADD: return visitFADD(N); in visit()
16441 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine()
16467 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
16548 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FADD, DL, VT, {N0, N1})) in visitFADD()
16553 return DAG.getNode(ISD::FADD, DL, VT, N1, N0); in visitFADD()
16591 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); in visitFADD()
16597 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); in visitFADD()
16623 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
16625 SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1); in visitFADD()
16626 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC); in visitFADD()
[all …]
H A DLegalizeFloatTypes.cpp78 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
1408 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult()
2040 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, NewLo); in ExpandFloatRes_XINT_TO_FP()
2626 case ISD::FADD: in PromoteFloatResult()
3068 case ISD::FADD: in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp2776 Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt); in ExpandLegalINT_TO_FP()
2785 Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, DestVT)) in ExpandLegalINT_TO_FP()
2854 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); in ExpandLegalINT_TO_FP()
3752 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) && in ExpandNode()
3756 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags); in ExpandNode()
4753 case ISD::FADD: in ConvertNodeToLibcall()
5429 case ISD::FADD: in PromoteNode()
H A DSelectionDAGDumper.cpp285 case ISD::FADD: return "fadd"; in getOperationName()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp531 ISD::FADD, ISD::FCEIL, ISD::FCOS, in AMDGPUTargetLowering()
619 ISD::STORE, ISD::FADD, in AMDGPUTargetLowering()
647 case ISD::FADD: in fnegFoldsIntoOpcode()
2386 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2463 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN()
2522 return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset); in LowerFROUND()
2547 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2687 return DAG.getNode(ISD::FADD, SL, VT, Mul, C, Flags); in getMad()
2741 R = DAG.getNode(ISD::FADD, DL, VT, R, FMA1, Flags); in LowerFLOGCommon()
2821 return DAG.getNode(ISD::FADD, SL, VT, Mul, ResultOffset); in LowerFLOGUnsafe()
[all …]
H A DAMDGPUTargetTransformInfo.cpp589 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
604 case ISD::FADD: in getArithmeticInstrCost()
H A DSIISelLowering.cpp209 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV, in SITargetLowering()
779 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FMINNUM_IEEE, in SITargetLowering()
801 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE}, in SITargetLowering()
812 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG}, in SITargetLowering()
814 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA}, in SITargetLowering()
896 ISD::FADD, in SITargetLowering()
5852 case ISD::FADD: in LowerOperation()
12622 case ISD::FADD: in isCanonicalized()
13407 case ISD::FADD: in performExtractVectorEltCombine()
14320 if (LHS.getOpcode() == ISD::FADD) { in performFAddCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1262 ISD != ISD::FADD) in getArithmeticReductionCost()
1319 case ISD::FADD: in getArithmeticReductionCost()
1740 case ISD::FADD: in getArithmeticInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
H A DAArch64SchedA57.td446 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
448 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
H A DAArch64SchedKryoDetails.td639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td34 defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp443 case ISD::FADD: in NVPTXTargetLowering()
731 setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD, in NVPTXTargetLowering()
746 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { in NVPTXTargetLowering()
2583 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign); in LowerFROUND32()
2614 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA, in LowerFROUND64()
5364 if (User->getOpcode() != ISD::FADD) in PerformFADDCombineWithOperands()
6019 case ISD::FADD: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td123 defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;

123