Searched refs:F32VT (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 7083 EVT F32VT = SrcVT.isVector() ? SrcVT.changeVectorElementType(MVT::f32) : in lowerFP_ROUND() local
7085 SDValue Rod = expandRoundInexactToOdd(F32VT, Src, DL, DAG); in lowerFP_ROUND()
11961 EVT F32VT = MagVT.isVector() in performFCopySignCombine() local
11965 SDValue MagAsVector = DAG.getNode(ISD::BITCAST, DL, F32VT, MagnitudeOp); in performFCopySignCombine()
12007 EVT F32VT = MagVT.isVector() in performFCopySignCombine() local
12011 SDValue SignAsVector = DAG.getNode(ISD::BITCAST, DL, F32VT, SignOp); in performFCopySignCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4656 MVT F32VT = MVT::getVectorVT(MVT::f32, SrcVT.getVectorNumElements()); in LowerVectorFP_TO_INT_SAT() local
4657 SrcVal = DAG.getNode(ISD::FP_EXTEND, DL, F32VT, SrcVal); in LowerVectorFP_TO_INT_SAT()
4660 if (F32VT.getSizeInBits() > 128) { in LowerVectorFP_TO_INT_SAT()
4662 F32VT = F32VT.getHalfNumVectorElementsVT(); in LowerVectorFP_TO_INT_SAT()
4664 SrcVT = F32VT; in LowerVectorFP_TO_INT_SAT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3511 MVT F32VT = SrcContainerVT.changeVectorElementType(MVT::f32); in lowerVectorXRINT_XROUND() local
3512 Src = DAG.getNode(RISCVISD::FP_EXTEND_VL, DL, F32VT, Src, Mask, VL); in lowerVectorXRINT_XROUND()
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