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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrConv.td58 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
59 [(set I32:$dst, (fp_to_sint F32:$src))],
63 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
64 [(set I32:$dst, (fp_to_uint F32:$src))],
68 defm I64_TRUNC_S_SAT_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins),
69 [(set I64:$dst, (fp_to_sint F32:$src))],
73 defm I64_TRUNC_U_SAT_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins),
74 [(set I64:$dst, (fp_to_uint F32:$src))],
100 def : Pat<(fp_to_sint_sat F32:$src, i32), (I32_TRUNC_S_SAT_F32 F32:$src)>;
101 def : Pat<(fp_to_uint_sat F32:$src, i32), (I32_TRUNC_U_SAT_F32 F32:$src)>;
[all …]
H A DWebAssemblyInstrFloat.td16 defm _F32 : I<(outs F32:$dst), (ins F32:$src), (outs), (ins),
17 [(set F32:$dst, (node F32:$src))],
27 defm _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
28 [(set F32:$dst, (node F32:$lhs, F32:$rhs))],
37 defm _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
38 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
70 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
71 (COPYSIGN_F64 F64:$lhs, (F64_PROMOTE_F32 F32:$rhs))>;
72 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
73 (COPYSIGN_F32 F32:$lhs, (F32_DEMOTE_F64 F64:$rhs))>;
[all …]
H A DWebAssemblyRuntimeLibcallSignatures.cpp564 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
565 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
568 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
572 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
576 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
580 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
585 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
601 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
613 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
624 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
[all …]
H A DWebAssemblyFastISel.cpp1105 bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64; in selectFCmp() local
1110 Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64; in selectFCmp()
1113 Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64; in selectFCmp()
1116 Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64; in selectFCmp()
1119 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64; in selectFCmp()
1122 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64; in selectFCmp()
1125 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64; in selectFCmp()
1128 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64; in selectFCmp()
1132 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64; in selectFCmp()
1136 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64; in selectFCmp()
[all …]
H A DWebAssemblyInstrMemory.td60 defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a, []>;
77 WebAssemblyLoad<F32, "f32.load_f16", 0xfc30, [HasHalfPrecision]>;
145 defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>;
177 WebAssemblyStore<F32, "f32.store_f16", 0xfc31, [HasHalfPrecision]>;
H A DWebAssemblyInstrInfo.td291 defm "": ARGUMENT<F32, f32>;
374 defm "" : LOCAL<F32, global_op32>;
391 defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
393 [(set F32:$res, fpimm:$imm)],
H A DWebAssemblyRegisterInfo.td65 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTypeUtilities.cpp24 .Case("f32", wasm::ValType::F32) in parseType()
39 .Case("f32", WebAssembly::BlockType::F32) in parseBlockType()
108 return wasm::ValType::F32; in regClassToValType()
H A DWebAssemblyMCTypeUtilities.h30 F32 = unsigned(wasm::ValType::F32), enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td446 def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>;
459 def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>;
461 def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>;
464 def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>;
466 def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>;
470 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
471 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
718 def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>;
719 def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>;
720 def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td480 defm VBRDU : VBRDm<"vbrdu", 0x8c, V64, F32, VM>;
1000 let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM>;
1006 let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM>;
1012 let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM>;
1018 let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM>;
1052 let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>;
1061 let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>;
1073 let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>;
1089 let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>;
1112 defm PVFADDUP : RVm<"pvfadd.up", 0xcc, V64, F32, VM, simm7fp>;
[all …]
H A DVEInstrInfo.td1044 defm LDU : LOADm<"ldu", 0x02, F32, f32, load>;
1102 defm STU : STOREm<"stu", 0x12, F32, f32, store>;
1129 defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>;
1321 defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32, cmov, simm7fp>;
1371 defm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd, simm7fp, mimmfp32>;
1376 defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>;
1381 defm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul, simm7fp, mimmfp32>;
1386 defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
1391 defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, cmpf, simm7fp, mimmfp32>;
1398 defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp286 static const LLT F32 = LLT::float32(); variable
1678 .legalFor({{F32, LocalPtr}, {F64, LocalPtr}}); in AMDGPULegalizerInfo()
1681 AtomicFMinFMax.legalFor({{F32, GlobalPtr},{F32, BufferFatPtr}}); in AMDGPULegalizerInfo()
1685 AtomicFMinFMax.legalFor({F32, FlatPtr}); in AMDGPULegalizerInfo()
3270 const LLT F32 = LLT::scalar(32); in getScaledLogInput() local
3272 F32, APFloat::getSmallestNormalized(APFloat::IEEEsingle())); in getScaledLogInput()
3276 auto Scale32 = B.buildFConstant(F32, 0x1.0p+32); in getScaledLogInput()
3277 auto One = B.buildFConstant(F32, 1.0); in getScaledLogInput()
3279 B.buildSelect(F32, IsLtSmallestNormal, Scale32, One, Flags); in getScaledLogInput()
3280 auto ScaledInput = B.buildFMul(F32, Src, ScaleFactor, Flags); in getScaledLogInput()
[all …]
H A DSISchedule.td32 // Conversion to or from F32 (but not converting F64 to or from F32)
34 // F16 or F32 transcendental instructions (these are quarter rate)
71 // F16 or F32 pseudo scalar transcendental instructions
H A DAMDGPULibFunc.cpp393 P.ArgType = AMDGPULibFunc::F32; P.VectorSize = 4; break; in getNextParam()
645 case 'f': res.ArgType = AMDGPULibFunc::F32; break; in parseItaniumParam()
752 case AMDGPULibFunc::F32: return "f"; in getItaniumTypeName()
898 P.ArgType = AMDGPULibFunc::F32; in getFromTy()
947 case AMDGPULibFunc::F32: T = Type::getFloatTy(C); break; in getIntrinsicParamType()
H A DAMDGPULibCalls.cpp862 if (getArgType(FInfo) == AMDGPULibFunc::F32) { in TDOFold()
982 double dval = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
1053 double V = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
1082 if (getArgType(FInfo) == AMDGPULibFunc::F32) { in fold_pow()
1357 if ((getArgType(fInfo) != AMDGPULibFunc::F32 && in fold_sincos()
1673 if (getArgType(FInfo) == AMDGPULibFunc::F32) { in evaluateCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseV1.td904 // ASIMD FP convert, long (F16 to F32)
907 // ASIMD FP convert, long (F32 to F64)
910 // ASIMD FP convert, narrow (F32 to F16)
913 // ASIMD FP convert, narrow (F64 to F32)
917 // ASIMD FP convert, other, D-form F32 and Q-form F64
921 // ASIMD FP convert, other, D-form F16 and Q-form F32
933 // ASIMD FP divide, F32
934 // ASIMD FP square root, F32
950 // ASIMD FP max/min, reduce, F32 and D-form F16
962 // ASIMD FP round, D-form F32 and Q-form F64
[all …]
H A DAArch64SchedNeoverseN2.td1064 // ASIMD FP convert, long (F16 to F32)
1067 // ASIMD FP convert, long (F32 to F64)
1070 // ASIMD FP convert, narrow (F32 to F16)
1073 // ASIMD FP convert, narrow (F64 to F32)
1077 // ASIMD FP convert, other, D-form F32 and Q-form F64
1081 // ASIMD FP convert, other, D-form F16 and Q-form F32
1092 // ASIMD FP divide, D-form, F32
1098 // ASIMD FP divide, Q-form, F32
1104 // ASIMD FP max/min, reduce, F32 and D-form F16
1119 // ASIMD FP round, D-form F32 and Q-form F64
[all …]
H A DAArch64SchedNeoverseN1.td672 // ASIMD FP convert, long (F16 to F32)
675 // ASIMD FP convert, long (F32 to F64)
678 // ASIMD FP convert, narrow (F32 to F16)
681 // ASIMD FP convert, narrow (F64 to F32)
685 // ASIMD FP convert, other, D-form F32 and Q-form F64
689 // ASIMD FP convert, other, D-form F16 and Q-form F32
701 // ASIMD FP divide, D-form, F32
702 // ASIMD FP square root, D-form, F32
709 // ASIMD FP divide, Q-form, F32
710 // ASIMD FP square root, Q-form, F32
[all...]
H A DAArch64SchedNeoverseV2.td1555 // ASIMD FP convert, long (F16 to F32)
1558 // ASIMD FP convert, long (F32 to F64)
1561 // ASIMD FP convert, narrow (F32 to F16)
1564 // ASIMD FP convert, narrow (F64 to F32)
1568 // ASIMD FP convert, other, D-form F32 and Q-form F64
1576 // ASIMD FP convert, other, D-form F16 and Q-form F32
1595 // ASIMD FP divide, D-form, F32
1601 // ASIMD FP divide, Q-form, F32
1607 // ASIMD FP max/min, reduce, F32 and D-form F16
1622 // ASIMD FP round, D-form F32 and Q-form F64
[all …]
H A DAArch64SchedA510.td1012 // Floating point associative add, F32
1031 // Floating point convert, long or narrow (F16 to F32 or F32 to F16)
1036 // Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32
1048 // Floating point base2 log, F32
1057 // Floating point convert to integer, F32
1071 // Floating point divide, F32
1099 // Floating point reciprocal estimate, F32
1113 // Floating point reduction, F32
1127 // Floating point round to integral, F32
1136 // Floating point square root, F32
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DDXILABI.h85 F32, enumerator
H A DAMDGPUMetadata.h110 F32 = 8, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp47 return wasm::ValType::F32; in toValType()
/freebsd/contrib/llvm-project/llvm/lib/Demangle/
H A DRustDemangle.cpp55 F32, enumerator
404 Type = BasicType::F32; in parseBasicType()
500 case BasicType::F32: in printBasicType()

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