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Searched refs:ExtendOpcode (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h51 unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT member
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp599 if (CurrentUse.ExtendOpcode == OpcodeForCandidate || in ChoosePreferredUse()
600 CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
613 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
615 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
624 if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT && in ChoosePreferredUse()
627 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ZEXT && in ChoosePreferredUse()
807 unsigned LoadOpc = getExtLoadOpcForExtend(Preferred.ExtendOpcode); in applyCombineExtendingLoads()
821 if (UseMI->getOpcode() == Preferred.ExtendOpcode || in applyCombineExtendingLoads()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18094 unsigned ExtendOpcode = Extend.getOpcode(); in performBuildShuffleExtendCombine() local
18095 bool IsSExt = ExtendOpcode == ISD::SIGN_EXTEND || in performBuildShuffleExtendCombine()
18096 ExtendOpcode == ISD::SIGN_EXTEND_INREG || in performBuildShuffleExtendCombine()
18097 ExtendOpcode == ISD::AssertSext; in performBuildShuffleExtendCombine()
18098 if (!IsSExt && ExtendOpcode != ISD::ZERO_EXTEND && in performBuildShuffleExtendCombine()
18099 ExtendOpcode != ISD::AssertZext && ExtendOpcode != ISD::AND) in performBuildShuffleExtendCombine()
18104 ExtendOpcode != ISD::SIGN_EXTEND && ExtendOpcode != ISD::ZERO_EXTEND) in performBuildShuffleExtendCombine()
27418 unsigned ExtendOpcode = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFixedLengthVectorIntDivideToSVE() local
27423 SDValue Op0 = DAG.getNode(ExtendOpcode, dl, WideVT, Op.getOperand(0)); in LowerFixedLengthVectorIntDivideToSVE()
27424 SDValue Op1 = DAG.getNode(ExtendOpcode, dl, WideVT, Op.getOperand(1)); in LowerFixedLengthVectorIntDivideToSVE()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp6577 ISD::NodeType ExtendOpcode = in WidenVecOp_CMP()
6579 LHS = DAG.getNode(ExtendOpcode, dl, ResVT, LHS); in WidenVecOp_CMP()
6580 RHS = DAG.getNode(ExtendOpcode, dl, ResVT, RHS);
6573 ISD::NodeType ExtendOpcode = WidenVecOp_CMP() local
H A DDAGCombiner.cpp12249 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in foldVSelectOfConstants() local
12250 SDValue ExtendedCond = DAG.getNode(ExtendOpcode, DL, VT, Cond); in foldVSelectOfConstants()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp53825 unsigned ExtendOpcode = Extend->getOpcode(); in combineToExtendCMOV() local
53842 if (VT != MVT::i16 && !(ExtendOpcode == ISD::SIGN_EXTEND && VT == MVT::i32)) in combineToExtendCMOV()
53848 if (TargetVT == MVT::i64 && ExtendOpcode != ISD::SIGN_EXTEND) in combineToExtendCMOV()
53851 CMovOp0 = DAG.getNode(ExtendOpcode, DL, ExtendVT, CMovOp0); in combineToExtendCMOV()
53852 CMovOp1 = DAG.getNode(ExtendOpcode, DL, ExtendVT, CMovOp1); in combineToExtendCMOV()
53859 Res = DAG.getNode(ExtendOpcode, DL, TargetVT, Res); in combineToExtendCMOV()