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Searched refs:ExtOpc (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp378 bool isRegOffOpcode(unsigned ExtOpc) const ;
379 unsigned getRegOffOpcode(unsigned ExtOpc) const;
380 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
853 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const { in getRegOffOpcode()
857 switch (ExtOpc) { in getRegOffOpcode()
862 const MCInstrDesc &D = HII->get(ExtOpc); in getRegOffOpcode()
870 switch (ExtOpc) { in getRegOffOpcode()
943 if (!isStoreImmediate(ExtOpc)) in getRegOffOpcode()
944 return ExtOpc; in getRegOffOpcode()
953 unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const { in getDirectRegReplacement()
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H A DHexagonBitSimplify.cpp2521 unsigned ExtOpc = 0; in simplifyExtractLow() local
2524 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2526 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2528 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2530 if (ExtOpc == 0) { in simplifyExtractLow()
2531 ExtOpc = in simplifyExtractLow()
2543 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2547 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2559 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2561 switch (ExtOpc) { in simplifyExtractLow()
H A DHexagonISelLoweringHVX.cpp1601 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth() local
1602 return DAG.getNode(ExtOpc, dl, ResTy, VecV); in resizeToWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp423 auto ExtOpc = ExtMI->getOpcode(); in matchExtUaddvToUaddlv() local
425 if (ExtOpc == TargetOpcode::G_ZEXT) in matchExtUaddvToUaddlv()
427 else if (ExtOpc == TargetOpcode::G_SEXT) in matchExtUaddvToUaddlv()
H A DAArch64PostLegalizerCombiner.cpp545 unsigned ExtOpc = IsZExt ? TargetOpcode::G_ZEXT : TargetOpcode::G_SEXT; in applyExtMulToMULL() local
548 Src1Reg = B.buildExtOrTrunc(ExtOpc, {HalfDstTy}, {Src1Reg}).getReg(0); in applyExtMulToMULL()
550 Src2Reg = B.buildExtOrTrunc(ExtOpc, {HalfDstTy}, {Src2Reg}).getReg(0); in applyExtMulToMULL()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp549 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
552 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
553 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
563 Opcode = ExtOpc; in buildExtOrTrunc()
H A DLegalizerHelper.cpp2759 unsigned ExtOpc = Opcode == TargetOpcode::G_CTTZ || in widenScalar() local
2763 auto MIBSrc = MIRBuilder.buildInstr(ExtOpc, {WideTy}, {SrcReg}); in widenScalar()
2975 unsigned ExtOpc = in widenScalar() local
2982 widenScalarSrc(MI, WideTy, 1, ExtOpc); in widenScalar()
2983 widenScalarSrc(MI, WideTy, 2, ExtOpc); in widenScalar()
3120 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
3122 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
3123 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
3126 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
H A DCombinerHelper.cpp752 static unsigned getExtLoadOpcForExtend(unsigned ExtOpc) { in getExtLoadOpcForExtend() argument
754 switch (ExtOpc) { in getExtLoadOpcForExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp1378 unsigned ExtOpc = TargetOpcode::G_ANYEXT; in legalizeCustom() local
1380 ExtOpc = TargetOpcode::G_SEXT; in legalizeCustom()
1382 ExtOpc = TargetOpcode::G_ZEXT; in legalizeCustom()
1385 Helper.widenScalarSrc(MI, sXLen, 1, ExtOpc); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp3821 Instruction::CastOps ExtOpc = Instruction::CastOps::CastOpsEnd; in visitCallInst() local
3823 ExtOpc = cast<CastInst>(Arg)->getOpcode(); in visitCallInst()
3825 (ExtOpc == Instruction::CastOps::ZExt)) in visitCallInst()
3829 Res = Builder.CreateCast(ExtOpc, Res, II->getType()); in visitCallInst()
H A DInstCombineCompares.cpp7856 unsigned ExtOpc = ExtI->getOpcode(); in visitICmpInst() local
7858 if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) || in visitICmpInst()
7859 (ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) { in visitICmpInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1927 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1930 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1932 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1944 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h803 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4612 unsigned ExtOpc = in lowerScalarSplat() local
4614 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
4676 unsigned ExtOpc = in lowerScalarInsert() local
4678 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarInsert()
10328 unsigned ExtOpc = in lowerVectorIntrinsicScalars() local
10330 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
10558 unsigned ExtOpc = in promoteVCIXScalar() local
10560 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in promoteVCIXScalar()
14042 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
14045 SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1511 unsigned ExtOpc = in PromoteOperand() local
1513 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
7483 unsigned ExtOpc = N0.getOpcode(); in visitAND() local
7486 (ExtOpc != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0Op0, VT)) && in visitAND()
7488 if (SDValue NewExt = DAG.FoldConstantArithmetic(ExtOpc, DL, VT, in visitAND()
7493 DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(0)), in visitAND()
13814 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
13826 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
13828 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
14148 ISD::NodeType ExtOpc, in tryToFoldExtOfLoad() argument
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H A DLegalizeIntegerTypes.cpp6112 unsigned ExtOpc = ISD::ANY_EXTEND; in PromoteIntRes_BUILD_VECTOR() local
6117 ExtOpc = NOutExtOpc; in PromoteIntRes_BUILD_VECTOR()
6118 Op = DAG.getNode(ExtOpc, dl, NOutVTElem, Op); in PromoteIntRes_BUILD_VECTOR()
H A DTargetLowering.cpp5788 ISD::NodeType ExtOpc = in LowerAsmOperandForConstraint() local
5791 ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); in LowerAsmOperandForConstraint()
9786 unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in expandAVG() local
9810 LHS = DAG.getNode(ExtOpc, dl, ExtVT, LHS); in expandAVG()
9811 RHS = DAG.getNode(ExtOpc, dl, ExtVT, RHS); in expandAVG()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp12382 unsigned ExtOpc, SDValue InputV, in lowerShuffleAsSpecificExtension() argument
12387 assert(ISD::isExtOpcode(ExtOpc) && "Unsupported extension"); in lowerShuffleAsSpecificExtension()
12428 InputV = getEXTEND_VECTOR_INREG(ExtOpc, DL, ExtVT, InputV, DAG); in lowerShuffleAsSpecificExtension()
12434 bool AnyExt = ExtOpc == ISD::ANY_EXTEND; in lowerShuffleAsSpecificExtension()
12437 if (ExtOpc == ISD::SIGN_EXTEND) in lowerShuffleAsSpecificExtension()
12623 unsigned ExtOpc = AnyExt ? ISD::ANY_EXTEND : ISD::ZERO_EXTEND; in lowerShuffleAsZeroOrAnyExtend() local
12624 return lowerShuffleAsSpecificExtension(DL, VT, Scale, Offset, ExtOpc, in lowerShuffleAsZeroOrAnyExtend()
20928 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
20935 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
20936 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
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H A DX86TargetTransformInfo.cpp3280 unsigned ExtOpc = in getCastInstrCost() local
3286 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp3817 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
3826 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
3831 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
3832 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18725 unsigned ExtOpc = !SeenZExtOrSExt in performBuildShuffleExtendCombine() local
18728 return DAG.getNode(ExtOpc, DL, VT, NBV); in performBuildShuffleExtendCombine()