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Searched refs:ExtOp (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp5239 unsigned ExtOp, TruncOp; in PromoteNode() local
5241 ExtOp = ISD::BITCAST; in PromoteNode()
5248 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
5254 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5258 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
5263 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5265 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
5271 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
5272 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
5281 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND in PromoteNode() local
[all …]
H A DLegalizeVectorOps.cpp603 unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in PromoteSETCC() local
608 Operands[0] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(0)); in PromoteSETCC()
609 Operands[1] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(1)); in PromoteSETCC()
H A DDAGCombiner.cpp17839 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
17841 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1538 MachineOperand ExtOp(EV); in insertInitializer() local
1549 .add(ExtOp); in insertInitializer()
1555 .add(ExtOp); in insertInitializer()
1560 .add(ExtOp) in insertInitializer()
1566 .add(ExtOp); in insertInitializer()
1574 .add(ExtOp) in insertInitializer()
1587 .add(ExtOp) in insertInitializer()
1592 .add(ExtOp); in insertInitializer()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineInternal.h224 Constant *getLosslessTrunc(Constant *C, Type *TruncTy, unsigned ExtOp) { in getLosslessTrunc() argument
227 ConstantFoldCastOperand(ExtOp, TruncC, C->getType(), DL); in getLosslessTrunc()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSSE.td5057 SDNode ExtOp, SDNode InVecOp> {
5060 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5069 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5074 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5083 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))),
5104 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
5114 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
5136 SDNode ExtOp> {
5138 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
5142 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
[all …]
H A DX86InstrAVX512.td10134 multiclass AVX512_pmovx_patterns_base<string OpcPrefix, SDNode ExtOp> {
10137 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))),
10142 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
10145 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
10151 def : Pat<(v32i16 (ExtOp (loadv32i8 addr:$src))),
10155 def : Pat<(v16i32 (ExtOp (loadv16i8 addr:$src))),
10157 def : Pat<(v16i32 (ExtOp (loadv16i16 addr:$src))),
10160 def : Pat<(v8i64 (ExtOp (loadv8i16 addr:$src))),
10163 def : Pat<(v8i64 (ExtOp (loadv8i32 addr:$src))),
10168 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
[all …]
H A DX86ISelLowering.cpp18191 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
18194 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
42460 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
42464 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
42492 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
42496 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
42547 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode() local
42550 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
57148 unsigned ExtOp = DAG.getOpcode_EXTEND_VECTOR_INREG(InOpcode); in combineEXTRACT_SUBVECTOR() local
57149 return DAG.getNode(ExtOp, DL, VT, Ext); in combineEXTRACT_SUBVECTOR()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h2194 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local
2199 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
2261 unsigned ExtOp = IsSigned ? Instruction::SExt : Instruction::ZExt; in getTypeBasedIntrinsicInstrCost() local
2265 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3010 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3016 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3100 ValueType TyQ, ValueType TyD, SDNode OpNode, SDPatternOperator ExtOp,
3105 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3106 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3113 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3118 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3170 SDNode OpNode, SDPatternOperator ExtOp, bit Commutable>
3175 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3734 SDNode OpNode, SDPatternOperator ExtOp, bit Commutable = 0> {
[all …]
H A DARMISelLowering.cpp12816 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
12817 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp526 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt() local
527 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
H A DLegalizerHelper.cpp2254 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); in widenScalarAddSubOverflow() local
2256 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); in widenScalarAddSubOverflow()
2327 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo() local
2328 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); in widenScalarMulo()
2329 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); in widenScalarMulo()
8275 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in lowerSMULH_UMULH() local
8281 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); in lowerSMULH_UMULH()
8282 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); in lowerSMULH_UMULH()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1632 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1633 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp581 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
582 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1560 auto PromoteMULO = [&](unsigned ExtOp) { in lowerOverflowArithmetic() argument
1566 LHS = DAG.getNode(ExtOp, DL, MVT::i16, LHS); in lowerOverflowArithmetic()
1567 RHS = DAG.getNode(ExtOp, DL, MVT::i16, RHS); in lowerOverflowArithmetic()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6454 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
6455 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
14930 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
14931 if (!ExtOp) in combineBVOfVecSExt()
14934 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp8663 unsigned ExtOp = CmpI->isSigned() ? Instruction::SExt : Instruction::ZExt; in lookThroughCast() local
8664 CastedTo = ConstantFoldCastOperand(ExtOp, C, SrcTy, DL); in lookThroughCast()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp7464 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP() local
7465 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp); in combineINT_TO_FP()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp8380 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
8384 if (ExtOp) in packTBLDVectorList()
8385 TblOps.push_back(ExtOp); in packTBLDVectorList()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp24742 SDValue ExtOp = Src->getOperand(0); in performSignExtendInRegCombine() local
24752 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(), in performSignExtendInRegCombine()
24753 ExtOp, DAG.getValueType(ExtVT)); in performSignExtendInRegCombine()