| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 104 ExtractElementInst *getShuffleExtract(ExtractElementInst *Ext0,
107 bool isExtractExtractCheap(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
111 void foldExtExtCmp(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
113 void foldExtExtBinop(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
380 ExtractElementInst *Ext0, ExtractElementInst *Ext1, in getShuffleExtract() argument
382 auto *Index0C = dyn_cast<ConstantInt>(Ext0->getIndexOperand()); in getShuffleExtract()
393 Type *VecTy = Ext0->getVectorOperand()->getType(); in getShuffleExtract()
396 TTI.getVectorInstrCost(*Ext0, VecTy, CostKind, Index0); in getShuffleExtract()
408 return Ext0; in getShuffleExtract()
417 return Ext0; in getShuffleExtract()
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| H A D | VPlanTransforms.cpp | 2920 [&](bool isZExt, VPWidenRecipe *Mul, VPWidenCastRecipe *Ext0, in tryToMatchAndCreateMulAccumulateReduction()
2926 Ext0 ? Ctx.Types.inferScalarType(Ext0->getOperand(0)) : RedTy; in tryToMatchAndCreateMulAccumulateReduction()
2933 if (Ext0) in tryToMatchAndCreateMulAccumulateReduction()
2934 ExtCost += Ext0->computeCost(VF, Ctx); in tryToMatchAndCreateMulAccumulateReduction()
2977 auto *Ext0 = in tryToMatchAndCreateMulAccumulateReduction() local
2981 if ((Ext->getOpcode() == Ext0->getOpcode() || Ext0 == Ext1) && in tryToMatchAndCreateMulAccumulateReduction()
2982 Ext0->getOpcode() == Ext1->getOpcode() && in tryToMatchAndCreateMulAccumulateReduction()
2983 IsMulAccValidAndClampRange(Ext0->getOpcode() == in tryToMatchAndCreateMulAccumulateReduction()
2985 Mul, Ext0, Ext1, Ext)) { in tryToMatchAndCreateMulAccumulateReduction()
2987 Ext0->getOpcode(), Ext0->getOperand(0), Ext->getResultType(), *Ext0, in tryToMatchAndCreateMulAccumulateReduction()
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| H A D | VPlanRecipes.cpp | 2726 auto *Ext0 = cast<VPWidenCastRecipe>(ExpressionRecipes[0]); in print() local
2727 O << Instruction::getOpcodeName(Ext0->getOpcode()) << " to " in print()
2728 << *Ext0->getResultType(); in print()
2753 auto *Ext0 = cast<VPWidenCastRecipe>(ExpressionRecipes[0]); in print() local
2754 O << " " << Instruction::getOpcodeName(Ext0->getOpcode()) << " to " in print()
2755 << *Ext0->getResultType() << "), ("; in print()
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| H A D | VPlan.h | 2817 VPExpressionRecipe(VPWidenCastRecipe *Ext0, VPWidenCastRecipe *Ext1, in VPExpressionRecipe() argument
2820 {Ext0, Ext1, Mul, Red}) {} in VPExpressionRecipe()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10380 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10388 SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
10392 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10396 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
13442 SDValue Ext0 = Mul.getOperand(0); in PerformVQDMULHCombine() local
13444 if (Ext0.getOpcode() != ISD::SIGN_EXTEND || in PerformVQDMULHCombine()
13447 EVT VecVT = Ext0.getOperand(0).getValueType(); in PerformVQDMULHCombine()
13465 DAG.getNode(ISD::ANY_EXTEND, DL, ExtVecVT, Ext0.getOperand(0)); in PerformVQDMULHCombine()
13482 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext0.getOperand(0), in PerformVQDMULHCombine()
17315 SDValue Ext0 = in PerformVECREDUCE_ADDCombine() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 18408 SDValue Ext0 = Op0.getOperand(0); in performUADDVAddCombine() local
18410 if (Ext0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVAddCombine()
18412 Ext0.getOperand(0) != Ext1.getOperand(0)) in performUADDVAddCombine()
18416 if (Ext0.getOperand(0).getValueType().getVectorNumElements() != in performUADDVAddCombine()
18419 if ((Ext0.getConstantOperandVal(1) != 0 || in performUADDVAddCombine()
18422 Ext0.getConstantOperandVal(1) != VT.getVectorNumElements())) in performUADDVAddCombine()
18426 return DAG.getNode(Opcode, SDLoc(A), VT, Ext0.getOperand(0)); in performUADDVAddCombine()
18456 SDValue Ext0 = Op0.getOperand(0); in performUADDVZextCombine() local
18458 EVT ExtVT0 = Ext0.getValueType(); in performUADDVZextCombine()
18467 DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1); in performUADDVZextCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 3146 Instruction *Ext0, *Ext1; in foldICmpAddConstant() local
3149 m_Add(m_CombineAnd(m_Instruction(Ext0), m_ZExtOrSExt(m_Value(Op0))), in foldICmpAddConstant()
3159 Res += APInt(BW, isa<ZExtInst>(Ext0) ? 1 : -1, /*isSigned=*/true); in foldICmpAddConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3808 auto Ext0 = B.buildFPExt(F32, Log, Flags); in legalizeFPow() local
3811 .addUse(Ext0.getReg(0)) in legalizeFPow()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44068 SDValue Ext0 = in SimplifyDemandedVectorEltsForTargetNode() local
44071 TLO.DAG.getNode(Opc, DL, Ext0.getValueType(), Ext0, Op.getOperand(1)); in SimplifyDemandedVectorEltsForTargetNode()
44094 SDValue Ext0 = extractSubVector(Op.getOperand(0), 0, TLO.DAG, DL, 256); in SimplifyDemandedVectorEltsForTargetNode() local
44095 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, Ext0.getValueType(), Ext0, in SimplifyDemandedVectorEltsForTargetNode()
46749 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
46753 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
46771 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in scalarizeExtEltFP() local
46778 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
59684 SDValue Ext0 = extractSubVector(InVec.getOperand(0), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
59687 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 14381 SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00); in foldSextSetcc() local
14383 return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); in foldSextSetcc()
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