| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 41 MCRegister ExecReg; member in __anon314e3b690111::SIOptimizeExecMaskingPreRA
148 if (CmpReg == Register(ExecReg)) { in optimizeVcndVcmpPair()
152 } else if (And->getOperand(2).getReg() != Register(ExecReg)) { in optimizeVcndVcmpPair()
212 .addReg(ExecReg) in optimizeVcndVcmpPair()
307 if (XorTermMI.getOperand(1).getReg() != Register(ExecReg)) in optimizeElseBranch()
318 I->getOperand(1).getReg() == Register(ExecReg)) in optimizeElseBranch()
331 for (MCRegUnit Unit : TRI->regunits(ExecReg)) { in optimizeElseBranch()
381 ExecReg = MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC); in run()
474 if (!(I->isFullCopy() && I->getOperand(1).getReg() == Register(ExecReg))) in run()
489 MRI->replaceRegWith(SavedExec, ExecReg); in run()
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| H A D | SIPreEmitPeephole.cpp | 93 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVccBranch() local
105 if (A->modifiesRegister(ExecReg, TRI)) in optimizeVccBranch()
120 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
124 if (Op1.getReg() != ExecReg) in optimizeVccBranch()
142 ModifiesExec |= M->modifiesRegister(ExecReg, TRI); in optimizeVccBranch()
184 .addReg(ExecReg); in optimizeVccBranch()
192 if (SReg == ExecReg) { in optimizeVccBranch()
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| H A D | SILateBranchLowering.cpp | 43 Register ExecReg; member in __anon03252fca0111::SILateBranchLowering
171 .addDef(ExecReg); in expandChainCall()
178 auto SetExec = BuildMI(*MI.getParent(), MI, DL, TII->get(MovOpc), ExecReg); in expandChainCall()
222 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in run()
273 ExecReg) in run()
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| H A D | SILowerI1Copies.cpp | 453 ExecReg = AMDGPU::EXEC_LO; in PhiLoweringHelper()
461 ExecReg = AMDGPU::EXEC; in PhiLoweringHelper()
798 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg); in buildMergeLaneMasks()
801 .addReg(ExecReg) in buildMergeLaneMasks()
816 .addReg(ExecReg); in buildMergeLaneMasks()
827 .addReg(ExecReg); in buildMergeLaneMasks()
840 .addReg(ExecReg); in buildMergeLaneMasks()
844 .addReg(CurMaskedReg ? CurMaskedReg : ExecReg); in buildMergeLaneMasks()
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| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 176 B.buildInstr(AndN2Op, {PrevMaskedReg}, {PrevRegCopy, ExecReg}); in buildMergeLaneMasks()
177 B.buildInstr(AndOp, {CurMaskedReg}, {ExecReg, CurRegCopy}); in buildMergeLaneMasks()
221 .addUse(ExecReg, RegState::Implicit); in lowerTemporalDivergence()
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| H A D | SILowerI1Copies.h | 58 Register ExecReg; variable
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| H A D | SIRegisterInfo.cpp | 114 Register ExecReg; member
136 ExecReg = AMDGPU::EXEC_LO; in SGPRSpillBuilder()
140 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
216 BuildMI(*MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg); in prepare()
218 BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes); in prepare()
236 auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in prepare()
260 auto I = BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg) in restore()
271 auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in restore()
311 auto Not0 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
314 auto Not1 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
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| H A D | AMDGPURegisterBankInfo.cpp | 795 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop() local
954 .addDef(ExecReg) in executeInWaterfallLoop()
955 .addReg(ExecReg) in executeInWaterfallLoop()
966 .addReg(ExecReg); in executeInWaterfallLoop()
971 .addDef(ExecReg) in executeInWaterfallLoop()
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| H A D | SIISelLowering.cpp | 5128 MCRegister ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in lowerWaveReduce() local
5133 BuildMI(BB, MI, DL, TII->get(MovOpc), ExecMask).addReg(ExecReg); in lowerWaveReduce()
5211 unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in lowerWaveReduce() local
5217 BuildMI(BB, I, DL, TII->get(MovOpc), LoopIterator).addReg(ExecReg); in lowerWaveReduce()
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