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Searched refs:EmitIR (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h90 bool EmitIR = true);
94 bool EmitIR = true);
98 bool EmitIR);
278 bool EmitIR = true);
301 bool EmitIR = true);
410 MachineIRBuilder &MIRBuilder, bool EmitIR = true);
416 bool EmitIR = true);
452 SPIRVType *SpvType, bool EmitIR,
458 SPIRVType *SpvType = nullptr, bool EmitIR = true);
478 SPIRVType *SpvType, bool EmitIR = true);
H A DSPIRVGlobalRegistry.cpp62 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) { in assignTypeToVReg() argument
64 getOrCreateSPIRVType(Type, MIRBuilder, AccessQual, EmitIR); in assignTypeToVReg()
299 bool EmitIR) { in buildConstantInt() argument
312 LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32); in buildConstantInt()
316 SPIRV::AccessQualifier::ReadWrite, EmitIR); in buildConstantInt()
318 if (EmitIR) { in buildConstantInt()
503 uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR, in getOrCreateIntCompositeOrNull() argument
508 if (Val || EmitIR) { in getOrCreateIntCompositeOrNull()
511 SpvScalConst = buildConstantInt(Val, MIRBuilder, SpvBaseType, EmitIR); in getOrCreateIntCompositeOrNull()
513 LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32); in getOrCreateIntCompositeOrNull()
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H A DSPIRVISelLowering.cpp135 bool EmitIR, SPIRVType *ResType, in createNewPtrType() argument
144 ResTy, MIB, SPIRV::AccessQualifier::ReadWrite, EmitIR); in createNewPtrType()