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Searched refs:EltSizeInBits (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3185 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in decomposeMulByConstant() local
3186 if (isOperationLegal(ISD::MUL, VT) && EltSizeInBits <= 32 && in decomposeMulByConstant()
3187 (EltSizeInBits != 32 || !Subtarget.isPMULLDSlow())) in decomposeMulByConstant()
4621 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in getPack() local
4622 bool UsePackUS = Subtarget.hasSSE41() || EltSizeInBits == 8; in getPack()
4625 (EltSizeInBits * 2) == OpVT.getScalarSizeInBits() && in getPack()
4627 assert((EltSizeInBits == 8 || EltSizeInBits == 16 || EltSizeInBits == 32) && in getPack()
4631 if (EltSizeInBits == 32) { in getPack()
4648 DAG.computeKnownBits(LHS).countMaxActiveBits() <= EltSizeInBits && in getPack()
4649 DAG.computeKnownBits(RHS).countMaxActiveBits() <= EltSizeInBits) in getPack()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DMemorySanitizer.cpp3222 Type *getMMXVectorTy(unsigned EltSizeInBits) { in getMMXVectorTy()
3224 assert(EltSizeInBits != 0 && (X86_MMXSizeInBits % EltSizeInBits) == 0 && in getMMXVectorTy()
3226 return FixedVectorType::get(IntegerType::get(*MS.C, EltSizeInBits), in getMMXVectorTy()
3227 X86_MMXSizeInBits / EltSizeInBits); in getMMXVectorTy()
3268 void handleVectorPackIntrinsic(IntrinsicInst &I, unsigned EltSizeInBits = 0) { in handleVectorPackIntrinsic()
3279 Type *T = isX86_MMX ? getMMXVectorTy(EltSizeInBits) : S1->getType(); in handleVectorPackIntrinsic()
3428 unsigned EltSizeInBits = 0) { in handleVectorPmaddIntrinsic()
3430 Type *ResTy = isX86_MMX ? getMMXVectorTy(EltSizeInBits * 2) : I.getType(); in handleVectorPmaddIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3085 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in SimplifyDemandedVectorElts() local
3168 unsigned Ofs = (i % Scale) * EltSizeInBits; in SimplifyDemandedVectorElts()
3169 SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits); in SimplifyDemandedVectorElts()
3182 if (!Known.Zero.extractBits(EltSizeInBits, SubElt * EltSizeInBits) in SimplifyDemandedVectorElts()
3265 } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() && in SimplifyDemandedVectorElts()
3705 APInt DemandedBits = APInt::getAllOnes(EltSizeInBits); in SimplifyDemandedVectorElts()
8065 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in expandROT() local
8077 isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) { in expandROT()
8092 SDValue BitWidthMinusOneC = DAG.getConstant(EltSizeInBits - 1, DL, ShVT); in expandROT()
8095 if (isPowerOf2_32(EltSizeInBits)) { in expandROT()
[all …]
H A DDAGCombiner.cpp8480 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in MatchRotate() local
8486 auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS, in MatchRotate()
8488 return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits; in MatchRotate()
25196 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in canCombineShuffleToExtendVectorInreg() local
25206 EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale); in canCombineShuffleToExtendVectorInreg()
25269 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in combineShuffleToZeroExtendVectorInReg() local
25331 EltSizeInBits *= Prescale; in combineShuffleToZeroExtendVectorInReg()
25334 *DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits), in combineShuffleToZeroExtendVectorInReg()
25405 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in combineTruncationShuffle() local
25430 if (EltSizeInBits != ExtSrcSizeInBits) in combineTruncationShuffle()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6815 unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); in lowerRotate() local
6823 isPowerOf2_32(EltSizeInBits)) in lowerRotate()
6841 } else if (isPowerOf2_32(EltSizeInBits)) { in lowerRotate()
6850 auto BitWidthMinusOneC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits - 1); in lowerRotate()
6853 if (isPowerOf2_32(EltSizeInBits)) { in lowerRotate()
6865 auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits); in lowerRotate()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DInstructions.cpp2426 ArrayRef<int> Mask, unsigned EltSizeInBits, unsigned MinSubElts, in isBitRotateMask() argument
2432 RotateAmt = EltRotateAmt * EltSizeInBits; in isBitRotateMask()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstructions.h2276 static bool isBitRotateMask(ArrayRef<int> Mask, unsigned EltSizeInBits,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3371 unsigned EltSizeInBits) { in isSimpleVIDSequence()
3380 assert(EltSizeInBits >= Op.getValueType().getScalarSizeInBits()); in isSimpleVIDSequence()
3412 int64_t ValDiff = SignExtend64(*Elt - PrevElt->first, EltSizeInBits); in isSimpleVIDSequence()
3457 int64_t Addend = SignExtend64(*Elt - ExpectedVal, EltSizeInBits); in isSimpleVIDSequence()
4953 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in isLegalBitRotate()
4955 if (!ShuffleVectorInst::isBitRotateMask(SVN->getMask(), EltSizeInBits, 2, in isLegalBitRotate()
4958 RotateVT = MVT::getVectorVT(MVT::getIntegerVT(EltSizeInBits * NumSubElts), in isLegalBitRotate()
3370 isSimpleVIDSequence(SDValue Op,unsigned EltSizeInBits) isSimpleVIDSequence() argument
4952 unsigned EltSizeInBits = VT.getScalarSizeInBits(); isLegalBitRotate() local