| /freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/ |
| H A D | DXILIntrinsicExpansion.cpp | 88 Value *Elt0 = Builder.CreateExtractElement(A, (uint64_t)0); in expandIntegerDot() local
90 Value *Result = Builder.CreateMul(Elt0, Elt1); in expandIntegerDot()
92 Elt0 = Builder.CreateExtractElement(A, I); in expandIntegerDot()
95 ArrayRef<Value *>{Elt0, Elt1, Result}, in expandIntegerDot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 119 auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0)); in applyExtractVecEltPairwiseAdd() local
121 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 960 Register Elt0 = MI.getSourceReg(0); in tryCombineMergeLike() local
961 LLT EltTy = MRI.getType(Elt0); in tryCombineMergeLike()
966 auto *Unmerge = findUnmergeThatDefinesReg(Elt0, EltSize, Elt0UnmergeIdx); in tryCombineMergeLike()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 2334 Value *Elt0 = Builder.CreateExtractElement(Vec, (uint64_t)0); in upgradeX86IntrinsicCall() local
2336 Elt0->getType()); in upgradeX86IntrinsicCall()
2337 Elt0 = Builder.CreateCall(Intr, Elt0); in upgradeX86IntrinsicCall()
2338 Rep = Builder.CreateInsertElement(Vec, Elt0, (uint64_t)0); in upgradeX86IntrinsicCall()
2447 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), in upgradeX86IntrinsicCall() local
2453 EltOp = Builder.CreateFAdd(Elt0, Elt1); in upgradeX86IntrinsicCall()
2455 EltOp = Builder.CreateFSub(Elt0, Elt1); in upgradeX86IntrinsicCall()
2457 EltOp = Builder.CreateFMul(Elt0, Elt1); in upgradeX86IntrinsicCall()
2459 EltOp = Builder.CreateFDiv(Elt0, Elt1); in upgradeX86IntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12482 size_t Elt0 = *FirstRealEltIter - FirstRealIndex; in isWideDUPMask() local
12485 if (Elt0 % NumEltsPerBlock != 0) in isWideDUPMask()
12490 if (BlockElts[I] >= 0 && (unsigned)BlockElts[I] != Elt0 + I) in isWideDUPMask()
12493 DupLaneOp = Elt0 / NumEltsPerBlock; in isWideDUPMask()
20150 SDValue Elt0 = N->getOperand(0), Elt1 = N->getOperand(1), in performBuildVectorCombine() local
20152 if (Elt0->getOpcode() == ISD::FP_ROUND && in performBuildVectorCombine()
20154 isa<ConstantSDNode>(Elt0->getOperand(1)) && in performBuildVectorCombine()
20156 Elt0->getConstantOperandVal(1) == Elt1->getConstantOperandVal(1) && in performBuildVectorCombine()
20157 Elt0->getOperand(0)->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in performBuildVectorCombine()
20160 isa<ConstantSDNode>(Elt0->getOperand(0)->getOperand(1)) && in performBuildVectorCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4151 SDValue Elt0 = Vec.getOperand(0); in performTruncateCombine() local
4152 EVT EltVT = Elt0.getValueType(); in performTruncateCombine()
4155 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4156 EltVT.changeTypeToInteger(), Elt0); in performTruncateCombine()
4159 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
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| H A D | SIISelLowering.cpp | 7423 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE() local
7429 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 })); in lowerVECTOR_SHUFFLE()
9217 SDValue Elt0 = Ops.pop_back_val(); in LowerINTRINSIC_W_CHAIN() local
9221 { Elt0, Lanes[0] }))); in LowerINTRINSIC_W_CHAIN()
13421 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, in performExtractVectorEltCombine() local
13426 DCI.AddToWorklist(Elt0.getNode()); in performExtractVectorEltCombine()
13428 return DAG.getNode(Opc, SL, ResVT, Elt0, Elt1, Vec->getFlags()); in performExtractVectorEltCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8759 SDValue Elt0 = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); in lowerEXTRACT_VECTOR_ELT()
8760 return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt0);
8757 SDValue Elt0 = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec); lowerEXTRACT_VECTOR_ELT() local
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