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Searched refs:ElemsPerVReg (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp490 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in costShuffleViaVRegSplitting() local
492 FixedVectorType::get(Tp->getElementType(), ElemsPerVReg)) in costShuffleViaVRegSplitting()
H A DRISCVISelLowering.cpp4357 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerBUILD_VECTOR() local
4359 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerBUILD_VECTOR()
4370 for (unsigned i = 0; i < VT.getVectorNumElements(); i += ElemsPerVReg) { in lowerBUILD_VECTOR()
4371 auto OneVRegOfOps = ArrayRef(BuildVectorOps).slice(i, ElemsPerVReg); in lowerBUILD_VECTOR()
4375 unsigned InsertIdx = (i / ElemsPerVReg) * NumOpElts; in lowerBUILD_VECTOR()
5423 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerShuffleViaVRegSplitting() local
5426 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerShuffleViaVRegSplitting()
9992 unsigned ElemsPerVReg = *VLEN / ElemVT.getFixedSizeInBits(); in lowerINSERT_VECTOR_ELT() local
9993 unsigned RemIdx = OrigIdx % ElemsPerVReg; in lowerINSERT_VECTOR_ELT()
9994 unsigned SubRegIdx = OrigIdx / ElemsPerVReg; in lowerINSERT_VECTOR_ELT()
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