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Searched refs:EFX_STATIC_ASSERT (Results 1 – 25 of 25) sorted by relevance

/freebsd/sys/dev/sfxge/common/
H A Dsiena_phy.c233 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); in siena_phy_get_link()
234 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); in siena_phy_get_link()
235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); in siena_phy_get_link()
236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); in siena_phy_get_link()
237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); in siena_phy_get_link()
238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); in siena_phy_get_link()
239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); in siena_phy_get_link()
240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); in siena_phy_get_link()
241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); in siena_phy_get_link()
242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); in siena_phy_get_link()
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H A Defx_nic.c341 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED == in efx_nic_probe()
343 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY == in efx_nic_probe()
345 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM == in efx_nic_probe()
347 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE == in efx_nic_probe()
349 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 == in efx_nic_probe()
351 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE == in efx_nic_probe()
353 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK == in efx_nic_probe()
355 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE == in efx_nic_probe()
645 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID == in efx_nic_get_fw_version()
647 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID == in efx_nic_get_fw_version()
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H A Def10_ev.c470 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); in ef10_ev_qcreate()
471 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); in ef10_ev_qcreate()
587 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS > in ef10_ev_qprime()
589 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS < in ef10_ev_qprime()
683 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS == in ef10_ev_qmoderate()
685 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START == in ef10_ev_qmoderate()
687 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START == in ef10_ev_qmoderate()
689 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF == in ef10_ev_qmoderate()
916 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN); in ef10_ev_rx()
917 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP); in ef10_ev_rx()
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H A Def10_filter.c127 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST == in ef10_filter_init()
129 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_HOST == in ef10_filter_init()
131 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_MAC == in ef10_filter_init()
133 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_PORT == in ef10_filter_init()
135 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_MAC == in ef10_filter_init()
137 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_LOC_PORT == in ef10_filter_init()
139 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_ETHER_TYPE == in ef10_filter_init()
141 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_INNER_VID == in ef10_filter_init()
143 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_OUTER_VID == in ef10_filter_init()
145 EFX_STATIC_ASSERT(EFX_FILTER_MATCH_IP_PROTO == in ef10_filter_init()
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H A Def10_rx.c345 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN == in efx_mcdi_rss_context_set_flags()
347 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH == in efx_mcdi_rss_context_set_flags()
349 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN == in efx_mcdi_rss_context_set_flags()
351 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH == in efx_mcdi_rss_context_set_flags()
353 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN == in efx_mcdi_rss_context_set_flags()
355 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH == in efx_mcdi_rss_context_set_flags()
357 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN == in efx_mcdi_rss_context_set_flags()
359 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH == in efx_mcdi_rss_context_set_flags()
675 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE == in ef10_rx_scale_key_set()
1031 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH)); in ef10_rx_qcreate()
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H A Defx_ev.c396 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); in efx_ev_qpoll()
397 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); in efx_ev_qpoll()
399 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); in efx_ev_qpoll()
400 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); in efx_ev_qpoll()
401 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); in efx_ev_qpoll()
402 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == in efx_ev_qpoll()
405 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == in efx_ev_qpoll()
1310 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); in siena_ev_qcreate()
1311 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); in siena_ev_qcreate()
H A Def10_phy.c45 EFX_STATIC_ASSERT(EFX_PHY_CAP_##_cap == MC_CMD_PHY_CAP_##_cap##_LBN) in mcdi_phy_decode_cap()
675 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_LEN <=
677 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_SFT9001_LEN <=
679 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MRSFP_LEN <=
681 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MEM_LEN <=
H A Dsiena_nic.c96 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); in siena_board_cfg()
447 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0); in siena_nic_reset()
761 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks) in siena_nic_register_test()
775 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks) in siena_nic_register_test()
H A Defx_mcdi.c1515 EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI); in efx_mcdi_get_phy_cfg()
1516 EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4); in efx_mcdi_get_phy_cfg()
1517 EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4); in efx_mcdi_get_phy_cfg()
1518 EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP); in efx_mcdi_get_phy_cfg()
1519 EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS); in efx_mcdi_get_phy_cfg()
1520 EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T); in efx_mcdi_get_phy_cfg()
1521 EFX_STATIC_ASSERT(MC_CMD_MEDIA_QSFP_PLUS == EFX_PHY_MEDIA_QSFP_PLUS); in efx_mcdi_get_phy_cfg()
1682 EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0); in efx_mcdi_bist_enable_offline()
1683 EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0); in efx_mcdi_bist_enable_offline()
2350 EFX_STATIC_ASSERT(EFX_PHY_MEDIA_INFO_PAGE_SIZE <= 0xFF); in efx_mcdi_phy_module_get_info()
H A Defx_vpd.c406 EFX_STATIC_ASSERT(TAG_NAME_END_DECODE == EFX_VPD_END); in efx_vpd_next_tag()
407 EFX_STATIC_ASSERT(TAG_NAME_ID_STRING_DECODE == EFX_VPD_ID); in efx_vpd_next_tag()
408 EFX_STATIC_ASSERT(TAG_NAME_VPD_R_DECODE == EFX_VPD_RO); in efx_vpd_next_tag()
409 EFX_STATIC_ASSERT(TAG_NAME_VPD_W_DECODE == EFX_VPD_RW); in efx_vpd_next_tag()
H A Dmedford2_nic.c149 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); in medford2_board_cfg()
H A Dmedford_nic.c145 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); in medford_board_cfg()
H A Defx_tunnel.c118 EFX_STATIC_ASSERT(sizeof (efx_dword_t) == in efx_mcdi_set_tunnel_encap_udp_ports()
172 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES == in efx_tunnel_init()
H A Dhunt_nic.c224 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); in hunt_board_cfg()
H A Def10_image.c465 EFX_STATIC_ASSERT(sizeof (*header) == EFX_IMAGE_HEADER_SIZE); in efx_check_unsigned_image()
466 EFX_STATIC_ASSERT(sizeof (*trailer) == EFX_IMAGE_TRAILER_SIZE); in efx_check_unsigned_image()
734 EFX_STATIC_ASSERT(sizeof (chunk_hdr) == SIGNED_IMAGE_CHUNK_HDR_LEN); in efx_build_signed_image_write_buffer()
H A Defx_port.c220 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__efx_loopback_type_name) == in efx_loopback_type_name()
H A Defx_rx.c1338 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS); in siena_rx_scale_tbl_set()
1339 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH)); in siena_rx_scale_tbl_set()
1608 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == in siena_rx_qcreate()
1613 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS)); in siena_rx_qcreate()
1614 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS)); in siena_rx_qcreate()
H A Defx_tx.c945 EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS == in siena_tx_qcreate()
950 EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS)); in siena_tx_qcreate()
H A Dmcdi_mon.c44 EFX_STATIC_ASSERT(MC_CMD_SENSOR_STATE_ ## _field \
H A Def10_nic.c677 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0); in efx_mcdi_free_vis()
678 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0); in efx_mcdi_free_vis()
1262 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES == in ef10_get_datapath_caps()
H A Dsiena_vpd.c89 EFX_STATIC_ASSERT(SIENA_MC_STATIC_CONFIG_VERSION == 0); in siena_vpd_get_static()
H A Defx_filter.c1325 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) == in siena_filter_init()
1381 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) == in siena_filter_fini()
H A Dsiena_nvram.c353 EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0); in siena_nvram_get_dynamic_cfg()
H A Def10_nvram.c672 EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK); in ef10_nvram_buffer_validate()
1252 EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK); in ef10_nvram_read_tlv_segment()
H A Defx.h45 #define EFX_STATIC_ASSERT(_cond) \ macro