Searched refs:EFX_MASK32 (Results 1 – 8 of 8) sorted by relevance
394 EFX_MASK32(EFX_RX_CLASS_IPV4_TCP), in efx_mcdi_rss_context_set_flags()397 EFX_MASK32(EFX_RX_CLASS_IPV4_UDP), in efx_mcdi_rss_context_set_flags()399 (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4), in efx_mcdi_rss_context_set_flags()402 EFX_MASK32(EFX_RX_CLASS_IPV6_TCP), in efx_mcdi_rss_context_set_flags()405 EFX_MASK32(EFX_RX_CLASS_IPV6_UDP), in efx_mcdi_rss_context_set_flags()407 (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6)); in efx_mcdi_rss_context_set_flags()
156 #define EFX_MASK32(_field) \ macro457 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))461 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))465 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))469 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))473 EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))1226 EFX_INSERT_FIELD32(_min, _max, _field, EFX_MASK32(_field))
417 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL)) in siena_intr_trigger()
802 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in ef10_ev_rx_packed_stream()947 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS); in ef10_ev_rx()
282 seq = emip->emi_seq++ & EFX_MASK32(MCDI_HEADER_SEQ); in efx_mcdi_request_start()386 (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { in efx_mcdi_read_response_header()777 (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { in efx_mcdi_ev_cpl()
161 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT); in siena_board_cfg()
126 #define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match)) in ef10_filter_init()
1892 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); in ef10_nic_board_cfg()