1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additional Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 /*- 33 * SPDX-License-Identifier: BSD-3-Clause 34 * 35 * Derived by information released by Intel under the following license: 36 * 37 * Copyright (c) 1999 - 2001, Intel Corporation 38 * 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions are met: 43 * 44 * 1. Redistributions of source code must retain the above copyright notice, 45 * this list of conditions and the following disclaimer. 46 * 47 * 2. Redistributions in binary form must reproduce the above copyright notice, 48 * this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 51 * 3. Neither the name of Intel Corporation nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 61 * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 62 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 64 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 */ 67 68 /* 69 * Marvell E1000 PHY registers 70 */ 71 72 #define E1000_MAX_REG_ADDRESS 0x1F 73 74 #define E1000_CR 0x00 /* control register */ 75 #define E1000_CR_SPEED_SELECT_MSB 0x0040 76 #define E1000_CR_COLL_TEST_ENABLE 0x0080 77 #define E1000_CR_FULL_DUPLEX 0x0100 78 #define E1000_CR_RESTART_AUTO_NEG 0x0200 79 #define E1000_CR_ISOLATE 0x0400 80 #define E1000_CR_POWER_DOWN 0x0800 81 #define E1000_CR_AUTO_NEG_ENABLE 0x1000 82 #define E1000_CR_SPEED_SELECT_LSB 0x2000 83 #define E1000_CR_LOOPBACK 0x4000 84 #define E1000_CR_RESET 0x8000 85 86 #define E1000_CR_SPEED_1000 0x0040 87 #define E1000_CR_SPEED_100 0x2000 88 #define E1000_CR_SPEED_10 0x0000 89 90 #define E1000_SR 0x01 /* status register */ 91 #define E1000_SR_EXTENDED 0x0001 92 #define E1000_SR_JABBER_DETECT 0x0002 93 #define E1000_SR_LINK_STATUS 0x0004 94 #define E1000_SR_AUTO_NEG 0x0008 95 #define E1000_SR_REMOTE_FAULT 0x0010 96 #define E1000_SR_AUTO_NEG_COMPLETE 0x0020 97 #define E1000_SR_PREAMBLE_SUPPRESS 0x0040 98 #define E1000_SR_EXTENDED_STATUS 0x0100 99 #define E1000_SR_100T2 0x0200 100 #define E1000_SR_100T2_FD 0x0400 101 #define E1000_SR_10T 0x0800 102 #define E1000_SR_10T_FD 0x1000 103 #define E1000_SR_100TX 0x2000 104 #define E1000_SR_100TX_FD 0x4000 105 #define E1000_SR_100T4 0x8000 106 107 #define E1000_ID1 0x02 /* ID register 1 */ 108 #define E1000_ID2 0x03 /* ID register 2 */ 109 #define E1000_ID_88E1000 0x01410C50 110 #define E1000_ID_88E1000S 0x01410C40 111 #define E1000_ID_88E1011 0x01410C20 112 #define E1000_ID_MASK 0xFFFFFFF0 113 114 #define E1000_AR 0x04 /* autonegotiation advertise reg */ 115 #define E1000_AR_SELECTOR_FIELD 0x0001 116 #define E1000_AR_10T 0x0020 117 #define E1000_AR_10T_FD 0x0040 118 #define E1000_AR_100TX 0x0080 119 #define E1000_AR_100TX_FD 0x0100 120 #define E1000_AR_100T4 0x0200 121 #define E1000_AR_PAUSE 0x0400 122 #define E1000_AR_ASM_DIR 0x0800 123 #define E1000_AR_REMOTE_FAULT 0x2000 124 #define E1000_AR_NEXT_PAGE 0x8000 125 #define E1000_AR_SPEED_MASK 0x01E0 126 127 /* Autonegotiation register bits for fiber cards (Alaska Only!) */ 128 #define E1000_FA_1000X_FD 0x0020 129 #define E1000_FA_1000X 0x0040 130 #define E1000_FA_SYM_PAUSE 0x0080 131 #define E1000_FA_ASYM_PAUSE 0x0100 132 #define E1000_FA_FAULT1 0x1000 133 #define E1000_FA_FAULT2 0x2000 134 #define E1000_FA_NEXT_PAGE 0x8000 135 136 #define E1000_LPAR 0x05 /* autoneg link partner abilities reg */ 137 #define E1000_LPAR_SELECTOR_FIELD 0x0001 138 #define E1000_LPAR_10T 0x0020 139 #define E1000_LPAR_10T_FD 0x0040 140 #define E1000_LPAR_100TX 0x0080 141 #define E1000_LPAR_100TX_FD 0x0100 142 #define E1000_LPAR_100T4 0x0200 143 #define E1000_LPAR_PAUSE 0x0400 144 #define E1000_LPAR_ASM_DIR 0x0800 145 #define E1000_LPAR_REMOTE_FAULT 0x2000 146 #define E1000_LPAR_ACKNOWLEDGE 0x4000 147 #define E1000_LPAR_NEXT_PAGE 0x8000 148 149 /* autoneg link partner ability register bits for fiber cards (Alaska Only!) */ 150 #define E1000_FPAR_1000X_FD 0x0020 151 #define E1000_FPAR_1000X 0x0040 152 #define E1000_FPAR_SYM_PAUSE 0x0080 153 #define E1000_FPAR_ASYM_PAUSE 0x0100 154 #define E1000_FPAR_FAULT1 0x1000 155 #define E1000_FPAR_FAULT2 0x2000 156 #define E1000_FPAR_ACK 0x4000 157 #define E1000_FPAR_NEXT_PAGE 0x8000 158 159 #define E1000_ER 0x06 /* autoneg expansion reg */ 160 #define E1000_ER_LP_NWAY 0x0001 161 #define E1000_ER_PAGE_RXD 0x0002 162 #define E1000_ER_NEXT_PAGE 0x0004 163 #define E1000_ER_LP_NEXT_PAGE 0x0008 164 #define E1000_ER_PAR_DETECT_FAULT 0x0100 165 166 #define E1000_NPTX 0x07 /* autoneg next page TX */ 167 #define E1000_NPTX_MSG_CODE_FIELD 0x0001 168 #define E1000_NPTX_TOGGLE 0x0800 169 #define E1000_NPTX_ACKNOWLDGE2 0x1000 170 #define E1000_NPTX_MSG_PAGE 0x2000 171 #define E1000_NPTX_NEXT_PAGE 0x8000 172 173 #define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */ 174 #define E1000_RNPR_MSG_CODE_FIELD 0x0001 175 #define E1000_RNPR_TOGGLE 0x0800 176 #define E1000_RNPR_ACKNOWLDGE2 0x1000 177 #define E1000_RNPR_MSG_PAGE 0x2000 178 #define E1000_RNPR_ACKNOWLDGE 0x4000 179 #define E1000_RNPR_NEXT_PAGE 0x8000 180 181 #define E1000_1GCR 0x09 /* 1000T (1G) control reg */ 182 #define E1000_1GCR_ASYM_PAUSE 0x0080 183 #define E1000_1GCR_1000T 0x0100 184 #define E1000_1GCR_1000T_FD 0x0200 185 #define E1000_1GCR_REPEATER_DTE 0x0400 186 #define E1000_1GCR_MS_VALUE 0x0800 187 #define E1000_1GCR_MS_ENABLE 0x1000 188 #define E1000_1GCR_TEST_MODE_NORMAL 0x0000 189 #define E1000_1GCR_TEST_MODE_1 0x2000 190 #define E1000_1GCR_TEST_MODE_2 0x4000 191 #define E1000_1GCR_TEST_MODE_3 0x6000 192 #define E1000_1GCR_TEST_MODE_4 0x8000 193 #define E1000_1GCR_SPEED_MASK 0x0300 194 195 #define E1000_1GSR 0x0A /* 1000T (1G) status reg */ 196 #define E1000_1GSR_IDLE_ERROR_CNT 0x0000 197 #define E1000_1GSR_ASYM_PAUSE_DIR 0x0100 198 #define E1000_1GSR_LP 0x0400 199 #define E1000_1GSR_LP_FD 0x0800 200 #define E1000_1GSR_REMOTE_RX_STATUS 0x1000 201 #define E1000_1GSR_LOCAL_RX_STATUS 0x2000 202 #define E1000_1GSR_MS_CONFIG_RES 0x4000 203 #define E1000_1GSR_MS_CONFIG_FAULT 0x8000 204 205 #define E1000_ESR 0x0F /* IEEE extended status reg */ 206 #define E1000_ESR_1000T 0x1000 207 #define E1000_ESR_1000T_FD 0x2000 208 #define E1000_ESR_1000X 0x4000 209 #define E1000_ESR_1000X_FD 0x8000 210 211 #define E1000_TX_POLARITY_MASK 0x0100 212 #define E1000_TX_NORMAL_POLARITY 0 213 214 #define E1000_AUTO_POLARITY_DISABLE 0x0010 215 216 #define E1000_SCR 0x10 /* special control register */ 217 #define E1000_SCR_JABBER_DISABLE 0x0001 218 #define E1000_SCR_POLARITY_REVERSAL 0x0002 219 #define E1000_SCR_SQE_TEST 0x0004 220 #define E1000_SCR_INT_FIFO_DISABLE 0x0008 221 #define E1000_SCR_CLK125_DISABLE 0x0010 222 #define E1000_SCR_MDI_MANUAL_MODE 0x0000 223 #define E1000_SCR_MDIX_MANUAL_MODE 0x0020 224 #define E1000_SCR_AUTO_X_1000T 0x0040 225 #define E1000_SCR_AUTO_X_MODE 0x0060 226 #define E1000_SCR_10BT_EXT_ENABLE 0x0080 227 #define E1000_SCR_MII_5BIT_ENABLE 0x0100 228 #define E1000_SCR_SCRAMBLER_DISABLE 0x0200 229 #define E1000_SCR_FORCE_LINK_GOOD 0x0400 230 #define E1000_SCR_ASSERT_CRS_ON_TX 0x0800 231 #define E1000_SCR_RX_FIFO_DEPTH_6 0x0000 232 #define E1000_SCR_RX_FIFO_DEPTH_8 0x1000 233 #define E1000_SCR_RX_FIFO_DEPTH_10 0x2000 234 #define E1000_SCR_RX_FIFO_DEPTH_12 0x3000 235 #define E1000_SCR_TX_FIFO_DEPTH_6 0x0000 236 #define E1000_SCR_TX_FIFO_DEPTH_8 0x4000 237 #define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 238 #define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 239 240 /* 88E3016 only */ 241 #define E1000_SCR_AUTO_MDIX 0x0030 242 #define E1000_SCR_SIGDET_POLARITY 0x0040 243 #define E1000_SCR_EXT_DISTANCE 0x0080 244 #define E1000_SCR_FEFI_DISABLE 0x0100 245 #define E1000_SCR_NLP_GEN_DISABLE 0x0800 246 #define E1000_SCR_LPNP 0x1000 247 #define E1000_SCR_NLP_CHK_DISABLE 0x2000 248 #define E1000_SCR_EN_DETECT 0x4000 249 250 #define E1000_SCR_EN_DETECT_MASK 0x0300 251 252 /* 88E1112 page 1 fiber specific control */ 253 #define E1000_SCR_FIB_TX_DIS 0x0008 254 #define E1000_SCR_FIB_SIGDET_POLARITY 0x0200 255 #define E1000_SCR_FIB_FORCE_LINK 0x0400 256 257 /* 88E1112 page 2 */ 258 #define E1000_SCR_MODE_MASK 0x0380 259 #define E1000_SCR_MODE_AUTO 0x0180 260 #define E1000_SCR_MODE_COPPER 0x0280 261 #define E1000_SCR_MODE_1000BX 0x0380 262 263 /* 88E1116 page 0 */ 264 #define E1000_SCR_POWER_DOWN 0x0004 265 /* 88E1116, 88E1149 page 2 */ 266 #define E1000_SCR_RGMII_POWER_UP 0x0008 267 268 /* 88E1116, 88E1149 page 3 */ 269 #define E1000_SCR_LED_STAT0_MASK 0x000F 270 #define E1000_SCR_LED_STAT1_MASK 0x00F0 271 #define E1000_SCR_LED_INIT_MASK 0x0F00 272 #define E1000_SCR_LED_LOS_MASK 0xF000 273 #define E1000_SCR_LED_STAT0(x) ((x) & E1000_SCR_LED_STAT0_MASK) 274 #define E1000_SCR_LED_STAT1(x) ((x) & E1000_SCR_LED_STAT1_MASK) 275 #define E1000_SCR_LED_INIT(x) ((x) & E1000_SCR_LED_INIT_MASK) 276 #define E1000_SCR_LED_LOS(x) ((x) & E1000_SCR_LED_LOS_MASK) 277 278 #define E1000_SSR 0x11 /* special status register */ 279 #define E1000_SSR_JABBER 0x0001 280 #define E1000_SSR_REV_POLARITY 0x0002 281 #define E1000_SSR_MDIX 0x0020 282 #define E1000_SSR_LINK 0x0400 283 #define E1000_SSR_SPD_DPLX_RESOLVED 0x0800 284 #define E1000_SSR_PAGE_RCVD 0x1000 285 #define E1000_SSR_DUPLEX 0x2000 286 #define E1000_SSR_SPEED 0xC000 287 #define E1000_SSR_10MBS 0x0000 288 #define E1000_SSR_100MBS 0x4000 289 #define E1000_SSR_1000MBS 0x8000 290 291 #define E1000_IER 0x12 /* interrupt enable reg */ 292 #define E1000_IER_JABBER 0x0001 293 #define E1000_IER_POLARITY_CHANGE 0x0002 294 #define E1000_IER_MDIX_CHANGE 0x0040 295 #define E1000_IER_FIFO_OVER_UNDERUN 0x0080 296 #define E1000_IER_FALSE_CARRIER 0x0100 297 #define E1000_IER_SYMBOL_ERROR 0x0200 298 #define E1000_IER_LINK_STAT_CHANGE 0x0400 299 #define E1000_IER_AUTO_NEG_COMPLETE 0x0800 300 #define E1000_IER_PAGE_RECEIVED 0x1000 301 #define E1000_IER_DUPLEX_CHANGED 0x2000 302 #define E1000_IER_SPEED_CHANGED 0x4000 303 #define E1000_IER_AUTO_NEG_ERR 0x8000 304 305 /* 88E1116, 88E1149 page 3, LED timer control. */ 306 #define E1000_PULSE_MASK 0x7000 307 #define E1000_PULSE_NO_STR 0 /* no pulse stretching */ 308 #define E1000_PULSE_21MS 1 /* 21 ms to 42 ms */ 309 #define E1000_PULSE_42MS 2 /* 42 ms to 84 ms */ 310 #define E1000_PULSE_84MS 3 /* 84 ms to 170 ms */ 311 #define E1000_PULSE_170MS 4 /* 170 ms to 340 ms */ 312 #define E1000_PULSE_340MS 5 /* 340 ms to 670 ms */ 313 #define E1000_PULSE_670MS 6 /* 670 ms to 1300 ms */ 314 #define E1000_PULSE_1300MS 7 /* 1300 ms to 2700 ms */ 315 #define E1000_PULSE_DUR(x) ((x) & E1000_PULSE_MASK) 316 317 #define E1000_BLINK_MASK 0x0700 318 #define E1000_BLINK_42MS 0 /* 42 ms */ 319 #define E1000_BLINK_84MS 1 /* 84 ms */ 320 #define E1000_BLINK_170MS 2 /* 170 ms */ 321 #define E1000_BLINK_340MS 3 /* 340 ms */ 322 #define E1000_BLINK_670MS 4 /* 670 ms */ 323 #define E1000_BLINK_RATE(x) ((x) & E1000_BLINK_MASK) 324 325 #define E1000_ISR 0x13 /* interrupt status reg */ 326 #define E1000_ISR_JABBER 0x0001 327 #define E1000_ISR_POLARITY_CHANGE 0x0002 328 #define E1000_ISR_MDIX_CHANGE 0x0040 329 #define E1000_ISR_FIFO_OVER_UNDERUN 0x0080 330 #define E1000_ISR_FALSE_CARRIER 0x0100 331 #define E1000_ISR_SYMBOL_ERROR 0x0200 332 #define E1000_ISR_LINK_STAT_CHANGE 0x0400 333 #define E1000_ISR_AUTO_NEG_COMPLETE 0x0800 334 #define E1000_ISR_PAGE_RECEIVED 0x1000 335 #define E1000_ISR_DUPLEX_CHANGED 0x2000 336 #define E1000_ISR_SPEED_CHANGED 0x4000 337 #define E1000_ISR_AUTO_NEG_ERR 0x8000 338 339 #define E1000_ESCR 0x14 /* extended special control reg */ 340 #define E1000_ESCR_FIBER_LOOPBACK 0x4000 341 #define E1000_ESCR_DOWN_NO_IDLE 0x8000 342 #define E1000_ESCR_TX_CLK_2_5 0x0060 343 #define E1000_ESCR_TX_CLK_25 0x0070 344 #define E1000_ESCR_TX_CLK_0 0x0000 345 346 #define E1000_RECR 0x15 /* RX error counter reg */ 347 348 #define E1000_EADR 0x16 /* extended address reg */ 349 350 #define E1000_LCR 0x18 /* LED control reg */ 351 #define E1000_LCR_LED_TX 0x0001 352 #define E1000_LCR_LED_RX 0x0002 353 #define E1000_LCR_LED_DUPLEX 0x0004 354 #define E1000_LCR_LINK 0x0008 355 #define E1000_LCR_BLINK_42MS 0x0000 356 #define E1000_LCR_BLINK_84MS 0x0100 357 #define E1000_LCR_BLINK_170MS 0x0200 358 #define E1000_LCR_BLINK_340MS 0x0300 359 #define E1000_LCR_BLINK_670MS 0x0400 360 #define E1000_LCR_PULSE_OFF 0x0000 361 #define E1000_LCR_PULSE_21_42MS 0x1000 362 #define E1000_LCR_PULSE_42_84MS 0x2000 363 #define E1000_LCR_PULSE_84_170MS 0x3000 364 #define E1000_LCR_PULSE_170_340MS 0x4000 365 #define E1000_LCR_PULSE_340_670MS 0x5000 366 #define E1000_LCR_PULSE_670_13S 0x6000 367 #define E1000_LCR_PULSE_13_26S 0x7000 368 369 /* The following register is found only on the 88E1011 Alaska PHY */ 370 #define E1000_ESSR 0x1B /* Extended PHY specific sts */ 371 #define E1000_ESSR_FIBER_LINK 0x2000 372 #define E1000_ESSR_GMII_COPPER 0x000f 373 #define E1000_ESSR_GMII_FIBER 0x0007 374 #define E1000_ESSR_TBI_COPPER 0x000d 375 #define E1000_ESSR_TBI_FIBER 0x0005 376