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Searched refs:DstVec (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp479 Register DstVec = DstIsLeft ? Left : Right; in matchINS() local
488 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
498 Register DstVec, SrcVec; in applyINS() local
500 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
504 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst); in applyINS()
H A DAArch64InstructionSelector.cpp5780 Register DstVec = ScalarToVec->getOperand(0).getReg(); in selectBuildVector() local
5792 PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB); in selectBuildVector()
5793 DstVec = PrevMI->getOperand(0).getReg(); in selectBuildVector()
5802 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
5822 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg); in selectBuildVector()
5845 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DVerifier.cpp3305 bool DstVec = DestTy->isVectorTy(); in visitUIToFPInst() local
3307 Check(SrcVec == DstVec, in visitUIToFPInst()
3314 if (SrcVec && DstVec) in visitUIToFPInst()
3328 bool DstVec = DestTy->isVectorTy(); in visitSIToFPInst() local
3330 Check(SrcVec == DstVec, in visitSIToFPInst()
3337 if (SrcVec && DstVec) in visitSIToFPInst()
3351 bool DstVec = DestTy->isVectorTy(); in visitFPToUIInst() local
3353 Check(SrcVec == DstVec, in visitFPToUIInst()
3359 if (SrcVec && DstVec) in visitFPToUIInst()
3373 bool DstVec = DestTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp7696 SDValue DstVec; in LowerBUILD_VECTORvXi1() local
7703 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH); in LowerBUILD_VECTORvXi1()
7708 DstVec = DAG.getBitcast(VecVT, Imm); in LowerBUILD_VECTORvXi1()
7709 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
7713 DstVec = DAG.getUNDEF(VT); in LowerBUILD_VECTORvXi1()
7716 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
7720 return DstVec; in LowerBUILD_VECTORvXi1()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13266 SDValue DstVec = DstIsLeft ? V1 : V2; in LowerVECTOR_SHUFFLE() local
13283 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()