| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 497 Register DstVec = DstIsLeft ? Left : Right; in matchINS() local
506 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
516 Register DstVec, SrcVec; in applyINS() local
518 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
522 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst); in applyINS()
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| H A D | AArch64InstructionSelector.cpp | 5940 Register DstVec = ScalarToVec->getOperand(0).getReg(); in selectBuildVector() local
5952 PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB); in selectBuildVector()
5953 DstVec = PrevMI->getOperand(0).getReg(); in selectBuildVector()
5962 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
5982 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg); in selectBuildVector()
6005 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 3550 Value *DstVec, *SrcVec; in foldInsExtVectorToShuffle() local
3553 m_InsertElt(m_Value(DstVec), in foldInsExtVectorToShuffle()
3576 bool NeedDstSrcSwap = isa<PoisonValue>(DstVec) && !isa<UndefValue>(SrcVec); in foldInsExtVectorToShuffle()
3583 std::swap(DstVec, SrcVec); in foldInsExtVectorToShuffle()
3609 nullptr, {DstVec, SrcVec}); in foldInsExtVectorToShuffle()
3639 DstVec = Builder.CreateShuffleVector(DstVec, ExtToVecMask); in foldInsExtVectorToShuffle()
3643 if (isa<UndefValue>(DstVec) && !isa<UndefValue>(SrcVec)) { in foldInsExtVectorToShuffle()
3645 std::swap(DstVec, SrcVec); in foldInsExtVectorToShuffle()
3648 Value *Shuf = Builder.CreateShuffleVector(DstVec, SrcVec, Mask); in foldInsExtVectorToShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 3444 bool DstVec = DestTy->isVectorTy(); in visitUIToFPInst() local
3446 Check(SrcVec == DstVec, in visitUIToFPInst()
3453 if (SrcVec && DstVec) in visitUIToFPInst()
3467 bool DstVec = DestTy->isVectorTy(); in visitSIToFPInst() local
3469 Check(SrcVec == DstVec, in visitSIToFPInst()
3476 if (SrcVec && DstVec) in visitSIToFPInst()
3490 bool DstVec = DestTy->isVectorTy(); in visitFPToUIInst() local
3492 Check(SrcVec == DstVec, in visitFPToUIInst()
3498 if (SrcVec && DstVec) in visitFPToUIInst()
3512 bool DstVec = DestTy->isVectorTy(); in visitFPToSIInst() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8060 SDValue DstVec; in LowerBUILD_VECTORvXi1() local
8067 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH); in LowerBUILD_VECTORvXi1()
8072 DstVec = DAG.getBitcast(VecVT, Imm); in LowerBUILD_VECTORvXi1()
8073 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
8077 DstVec = DAG.getUNDEF(VT); in LowerBUILD_VECTORvXi1()
8080 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
8084 return DstVec; in LowerBUILD_VECTORvXi1()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14099 SDValue DstVec = DstIsLeft ? V1 : V2; in LowerVECTOR_SHUFFLE() local
14116 ISD::INSERT_VECTOR_ELT, DL, VT, DstVec, in LowerVECTOR_SHUFFLE()
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