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Searched refs:DstVT (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1920 ValueType DstVT> {
1939 !if(!eq(DstVT.Size, 1),
1962 class getOutsDPP <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
1964 !if(!eq(DstVT.Size, 1),
1971 class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
1973 !if(!eq(DstVT.Size, 1),
1981 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1982 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2050 class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
2052 !if(!eq(DstVT.Size, 1),
[all …]
H A DVOPInstructions.td143 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
610 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
827 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
1076 !subst(P.DstRC, P.DstVT, tmp)));
1123 list<dag> ret3 = [(set P.DstVT:$vdst,
1128 list<dag> ret2 = [(set P.DstVT:$vdst,
1132 list<dag> ret1 = [(set P.DstVT:$vdst,
1148 list<dag> ret3 = [(set P.DstVT:$vdst,
1153 list<dag> ret2 = [(set P.DstVT:$vdst,
1158 list<dag> ret1 = [(set P.DstVT:$vdst,
[all …]
H A DVOP3PInstructions.td563 bit NoDstOverlap = !gt(DstVT.Size, 128);
570 let Src2VT = DstVT;
861 GCNPat < (P.DstVT (node
866 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
870 GCNPat < (P.DstVT (node
875 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
879 GCNPat < (P.DstVT (node
884 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
1279 …def : GCNPat <(P.DstVT !setdagop(!con(P.WmmaInPat, !if(IsGFX11OpselIntrinsic, (ins 0), (ins))), no…
1280 (P.DstVT !setdagop(P.WmmaOutPat, !cast<Instruction>(Inst#"_twoaddr")))>;
[all …]
H A DVOP1Instructions.td52 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
646 class VOPProfile_Base_CVT_F_F8_ByteSel<ValueType DstVT> : VOPProfile<[DstVT, i32, untyped, untyped]…
H A DVOP2Instructions.td72 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
132 [(set P.DstVT:$vdst,
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
467 0 /*Src2HasMods*/, DstVT>.ret;
668 let DstRC64 = getVALUDstForVT<DstVT>.ret;
951 (P.DstVT (op (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
H A DVOP3Instructions.td111 let HasOMod = !ne(DstVT.Value, f16.Value);
998 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
999 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
1000 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
699 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1246 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1248 if (SrcVT != DstVT) { in X86SelectRet()
1261 if (SrcVT != DstVT) { in X86SelectRet()
1265 fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1534 EVT DstVT = TLI.getValueType(DL, I->getType()); in X86SelectZExt() local
1535 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1553 if (DstVT == MVT::i64) { in X86SelectZExt()
[all …]
H A DX86SelectionDAGInfo.cpp251 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
255 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp4269 auto MakeBroadcastOp = [&](SDValue Op, MVT OpVT, MVT DstVT) { in getAVX512Node() argument
4277 if (OpVT == DstVT && Op.getOpcode() != ISD::BITCAST) in getAVX512Node()
4286 return DAG.getConstant(SplatValue, DL, DstVT); in getAVX512Node()
4293 MVT DstVT = VT; in getAVX512Node() local
4295 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node()
4306 if (SDValue BroadcastOp = MakeBroadcastOp(Op, OpVT, DstVT)) { in getAVX512Node()
4316 SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps); in getAVX512Node()
10059 static bool matchShuffleAsVTRUNC(MVT &SrcVT, MVT &DstVT, MVT VT, in matchShuffleAsVTRUNC() argument
10081 DstVT = MVT::getIntegerVT(EltSizeInBits); in matchShuffleAsVTRUNC()
10084 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
[all …]
H A DX86ISelDAGToDAG.cpp1356 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1359 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1367 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1383 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1394 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1412 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1415 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1423 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1439 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1468 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
[all …]
H A DX86InstrAVX512.td7224 RegisterClass SrcRC, X86VectorVTInfo DstVT,
7228 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7231 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
7232 (ins DstVT.FRC:$src1, SrcRC:$src),
7236 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
7237 (ins DstVT.FRC:$src1, x86memop:$src),
7241 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
7242 (ins DstVT.RC:$src1, SrcRC:$src2),
7244 [(set DstVT.RC:$dst,
7245 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1063 MVT DstVT; in SelectIToFP() local
1065 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1068 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1089 if (DstVT == MVT::f32) in SelectIToFP()
1112 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1134 if (DstVT == MVT::f32) in SelectIToFP()
1188 MVT DstVT, SrcVT; in SelectFPToI() local
1190 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1193 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1197 if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() && in SelectFPToI()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1503 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1505 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1506 !DstVT.isSimple()) in selectCast()
1511 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1523 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1541 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1547 if (SrcVT == DstVT) { in selectBitCast()
1553 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1908 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
1909 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
H A DTargetLowering.cpp698 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
699 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
703 unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
707 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
728 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
746 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
856 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
858 DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
860 return DAG.getBitcast(DstVT, Src); in SimplifyMultipleUseDemandedBits()
8174 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3589 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3591 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3646 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3649 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3654 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3657 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3662 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3664 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3666 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3668 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
H A DMipsFastISel.cpp1093 MVT DstVT, SrcVT; in selectFPToInt() local
1098 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1101 if (DstVT != MVT::i32) in selectFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h241 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1888 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree()
1891 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
1892 !DstVT.isInteger()) in isTruncateFree()
1895 unsigned DestBits = DstVT.getSizeInBits(); in isTruncateFree()
1929 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt()
1930 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
2912 MVT DstVT = Op.getSimpleValueType(); in lowerFP_TO_INT_SAT()
2917 if (!DstVT.isVector()) { in lowerFP_TO_INT_SAT()
2926 if (SatVT == DstVT) in lowerFP_TO_INT_SAT()
2928 else if (DstVT in lowerFP_TO_INT_SAT()
2911 MVT DstVT = Op.getSimpleValueType(); lowerFP_TO_INT_SAT() local
5794 MVT DstVT = VT0.changeVectorElementTypeToInteger(); LowerIS_FPCLASS() local
11412 MVT DstVT = Op.getSimpleValueType(); lowerVPFPIntConvOp() local
15393 EVT DstVT = N->getValueType(0); performFP_TO_INT_SATCombine() local
[all...]
H A DRISCVISelLowering.h499 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
502 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2725 static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, in truncateVectorWithNARROW() argument
2730 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2737 assert(DstVT.getVectorNumElements() == NumElems && "Illegal truncation"); in truncateVectorWithNARROW()
2738 assert(SrcSizeInBits > DstVT.getSizeInBits() && "Illegal truncation"); in truncateVectorWithNARROW()
2759 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
2763 return DAG.getBitcast(DstVT, Res); in truncateVectorWithNARROW()
2773 return truncateVectorWithNARROW(DstVT, Res, DL, DAG); in truncateVectorWithNARROW()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1528 MVT DstVT; in SelectIToFP() local
1530 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1573 MVT DstVT; in SelectFPToI() local
1575 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp6204 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
6212 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in CombineVMOVDRRCandidateWithVecOp()
6222 unsigned DstNumElt = DstVT.getVectorNumElements(); in CombineVMOVDRRCandidateWithVecOp()
6237 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
6240 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
6258 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
6261 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
6262 return MoveToHPR(SDLoc(N), DAG, MVT::i32, DstVT.getSimpleVT(), in ExpandBITCAST()
6265 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
6268 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
[all …]
H A DARMISelLowering.h461 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1582 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1605 DstVT = MVT::i32; in tryIndexedLoad()
1609 if (DstVT == MVT::i64) in tryIndexedLoad()
1615 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1618 DstVT = MVT::i32; in tryIndexedLoad()
1622 if (DstVT == MVT::i64) in tryIndexedLoad()
1628 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1631 DstVT = MVT::i32; in tryIndexedLoad()
1652 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1471 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
1474 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
1479 if (SrcVT.bitsLT(DstVT)) in OptimizeNoopCopyExpression()
1488 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
1490 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
1493 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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