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Searched refs:DstVT (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp97 auto DstVT = DstTy.getSimpleVT(); in getCastInstrCost() local
108 if ((SrcVT == MVT::v8i8 && DstVT == MVT::v8i16) || in getCastInstrCost()
109 (SrcVT == MVT::v4i16 && DstVT == MVT::v4i32) || in getCastInstrCost()
110 (SrcVT == MVT::v2i32 && DstVT == MVT::v2i64)) { in getCastInstrCost()
115 if ((SrcVT == MVT::v4i8 && DstVT == MVT::v4i32) || in getCastInstrCost()
116 (SrcVT == MVT::v2i16 && DstVT == MVT::v2i64)) { in getCastInstrCost()
137 ConvertCostTableLookup(ConversionTbl, ISD, DstVT, SrcVT)) { in getCastInstrCost()
H A DWebAssemblyISelLowering.cpp3135 static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, in truncateVectorWithNARROW() argument
3140 if (SrcVT == DstVT) in truncateVectorWithNARROW()
3147 assert(DstVT.getVectorNumElements() == NumElems && "Illegal truncation"); in truncateVectorWithNARROW()
3148 assert(SrcSizeInBits > DstVT.getSizeInBits() && "Illegal truncation"); in truncateVectorWithNARROW()
3169 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
3173 return DAG.getBitcast(DstVT, Res); in truncateVectorWithNARROW()
3183 return truncateVectorWithNARROW(DstVT, Res, DL, DAG); in truncateVectorWithNARROW()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1941 // dst's opsel bit. Use a dummy value for DstVT if getting the mod for a src operand besides 0.
1943 class getSrc0Mod <ValueType VT, ValueType DstVT, bit IsTrue16 = 0, bit IsFake16 = 1> {
1956 Operand ret = !if(!and(IsTrue16, !eq(DstVT.Size, 16)), T16Dst, Normal);
1991 // dst's opsel bit. Use a dummy value for DstVT if getting the mod for a src operand besides 0.
1993 class getSrc0ModVOP3DPP <ValueType VT, ValueType DstVT, bit IsFake16 = 1> {
2007 Operand ret = !if(!and(!not(IsFake16), !eq(DstVT.Size, 16)), T16Dst, Normal);
2207 ValueType DstVT> {
2226 !if(!eq(DstVT.Size, 1),
2270 class getOutsDPP <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
2272 !if(!eq(DstVT.Size, 1),
[all …]
H A DVOPInstructions.td146 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
738 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
982 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
1273 !subst(P.DstRC, P.DstVT, tmp)));
1320 list<dag> ret3 = [(set P.DstVT:$vdst,
1325 list<dag> ret2 = [(set P.DstVT:$vdst,
1329 list<dag> ret1 = [(set P.DstVT:$vdst,
1345 list<dag> ret3 = [(set P.DstVT:$vdst,
1350 list<dag> ret2 = [(set P.DstVT:$vdst,
1355 list<dag> ret1 = [(set P.DstVT:$vdst,
[all …]
H A DVOPCInstructions.td53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
94 let DstRC = getVALUDstForVT<DstVT, 1 /*IsTrue16*/, 0 /*IsVOP3Encoding*/>.ret;
107 let DstRC64 = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 1/*IsVOP3Encoding*/>.ret;
111 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
114 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
120 let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
133 let DstRC64 = getVALUDstForVT<DstVT>.ret;
137 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
140 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret;
183 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
[all …]
H A DVOP2Instructions.td86 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
148 [(set P.DstVT:$vdst,
154 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
420 let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;
425 let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
456 let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;
461 let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
530 0 /*Src2HasMods*/, DstVT>.ret;
567 let DstRC64 = getVALUDstForVT<DstVT, 1/*IsTrue*/, 1/*IsVOP3Encoding*/>.ret;
573 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
[all …]
H A DVOP3PInstructions.td629 bit NoDstOverlap = !gt(DstVT.Size, 128);
636 let Src2VT = DstVT;
1196 GCNPat < (P.DstVT (node
1201 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
1205 GCNPat < (P.DstVT (node
1210 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
1214 GCNPat < (P.DstVT (node
1219 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
1758 …def : GCNPat <(P.DstVT !setdagop(!con(P.WmmaInPat, !if(IsGFX11OpselIntrinsic, (ins 0), (ins))), no…
1759 (P.DstVT !setdagop(P.WmmaOutPat, !cast<Instruction>(Inst#"_twoaddr")))>;
[all …]
H A DVOP1Instructions.td52 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
115 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
117 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
687 class VOPProfile_Base_CVT_F_F8_ByteSel<ValueType DstVT, bit _HasClamp = 0> :
688 VOPProfile<[DstVT, i32, untyped, untyped]> {
H A DVOP3Instructions.td120 let HasOMod = !ne(DstVT.Value, f16.Value);
668 HasModifiers, DstVT>.ret);
1493 1/*HasSrc2Mods*/, DstVT>.ret;
1639 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
1640 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
1641 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, Register Src, EVT SrcVT,
700 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, Register Src, in X86FastEmitExtend() argument
702 Register RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1245 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1247 if (SrcVT != DstVT) { in X86SelectRet()
1260 if (SrcVT != DstVT) { in X86SelectRet()
1264 fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1535 EVT DstVT = TLI.getValueType(DL, I->getType()); in X86SelectZExt() local
1536 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1554 if (DstVT == MVT::i64) { in X86SelectZExt()
[all …]
H A DX86SelectionDAGInfo.cpp310 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
314 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp4501 auto MakeBroadcastOp = [&](SDValue Op, MVT OpVT, MVT DstVT) { in getAVX512Node() argument
4509 if (OpVT == DstVT && Op.getOpcode() != ISD::BITCAST) in getAVX512Node()
4518 return DAG.getConstant(SplatValue, DL, DstVT); in getAVX512Node()
4525 MVT DstVT = VT; in getAVX512Node() local
4527 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node()
4538 if (SDValue BroadcastOp = MakeBroadcastOp(Op, OpVT, DstVT)) { in getAVX512Node()
4548 SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps); in getAVX512Node()
10557 static bool matchShuffleAsVTRUNC(MVT &SrcVT, MVT &DstVT, MVT VT, in matchShuffleAsVTRUNC() argument
10579 DstVT = MVT::getIntegerVT(EltSizeInBits); in matchShuffleAsVTRUNC()
10582 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
[all …]
H A DX86ISelDAGToDAG.cpp1400 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1403 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1411 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1427 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1438 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1456 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1459 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1467 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1483 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1512 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
[all …]
H A DX86InstrAVX512.td7235 RegisterClass SrcRC, X86VectorVTInfo DstVT,
7239 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7242 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
7243 (ins DstVT.FRC:$src1, SrcRC:$src),
7247 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
7248 (ins DstVT.FRC:$src1, x86memop:$src),
7252 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
7253 (ins DstVT.RC:$src1, SrcRC:$src2),
7255 [(set DstVT.RC:$dst,
7256 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1051 MVT DstVT; in SelectIToFP() local
1053 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1056 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1077 if (DstVT == MVT::f32) in SelectIToFP()
1100 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1122 if (DstVT == MVT::f32) in SelectIToFP()
1176 MVT DstVT, SrcVT; in SelectFPToI() local
1178 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1181 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1185 if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() && in SelectFPToI()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1825 EVT DstVT = Node->getValueType(0); in ExpandUINT_TO_FLOAT() local
1859 if ((!IsStrict && !TLI.isOperationLegalOrCustom(ISD::FMUL, DstVT)) || in ExpandUINT_TO_FLOAT()
1860 (IsStrict && !TLI.isOperationLegalOrCustom(ISD::STRICT_FMUL, DstVT))) { in ExpandUINT_TO_FLOAT()
1869 Result = DAG.getNode(ISD::STRICT_FP_ROUND, DL, {DstVT, MVT::Other}, in ExpandUINT_TO_FLOAT()
1875 Result = DAG.getNode(ISD::FP_ROUND, DL, DstVT, UIToFP, TargetZero); in ExpandUINT_TO_FLOAT()
1891 SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, DstVT); in ExpandUINT_TO_FLOAT()
1901 SDValue fHI = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL, {DstVT, MVT::Other}, in ExpandUINT_TO_FLOAT()
1903 fHI = DAG.getNode(ISD::STRICT_FMUL, DL, {DstVT, MVT::Other}, in ExpandUINT_TO_FLOAT()
1905 SDValue fLO = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL, {DstVT, MVT::Other}, in ExpandUINT_TO_FLOAT()
1913 DAG.getNode(ISD::STRICT_FADD, DL, {DstVT, MVT::Other}, {TF, fHI, fLO}); in ExpandUINT_TO_FLOAT()
[all …]
H A DFastISel.cpp1443 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1445 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1446 !DstVT.isSimple()) in selectCast()
1451 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1463 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1481 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1487 if (SrcVT == DstVT) { in selectBitCast()
1493 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1853 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
1854 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
H A DTargetLowering.cpp725 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
726 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
730 unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
734 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
755 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
773 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
911 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
913 DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
915 return DAG.getBitcast(DstVT, Src); in SimplifyMultipleUseDemandedBits()
8392 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3536 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3538 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3593 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3596 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3601 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3604 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3609 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3611 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3613 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3615 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
H A DMipsFastISel.cpp1105 MVT DstVT, SrcVT; in selectFPToInt() local
1110 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1113 if (DstVT != MVT::i32) in selectFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h47 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
50 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
H A DRISCVISelLowering.cpp2072 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree()
2075 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
2076 !DstVT.isInteger()) in isTruncateFree()
2079 unsigned DestBits = DstVT.getSizeInBits(); in isTruncateFree()
2113 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt()
2114 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
3074 MVT DstVT = Op.getSimpleValueType(); in lowerFP_TO_INT_SAT() local
3079 if (!DstVT.isVector()) { in lowerFP_TO_INT_SAT()
3088 if (SatVT == DstVT) in lowerFP_TO_INT_SAT()
3090 else if (DstVT == MVT::i64 && SatVT == MVT::i32) in lowerFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1578 MVT DstVT; in SelectIToFP() local
1580 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1615 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1626 MVT DstVT; in SelectFPToI() local
1628 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1649 Register IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp6270 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
6278 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in CombineVMOVDRRCandidateWithVecOp()
6288 unsigned DstNumElt = DstVT.getVectorNumElements(); in CombineVMOVDRRCandidateWithVecOp()
6303 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
6306 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
6323 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
6326 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
6327 return MoveToHPR(SDLoc(N), DAG, MVT::i32, DstVT.getSimpleVT(), in ExpandBITCAST()
6330 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
6335 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h289 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;

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