Searched refs:DstSubIdx (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 80 unsigned DstSubIdx = 0; in isCrossCopy() local
84 DstSubIdx = MI.getOperand(3).getImm(); in isCrossCopy()
88 DstSubIdx = MI.getOperand(OpNum+1).getImm(); in isCrossCopy()
98 if (SrcSubIdx && DstSubIdx) in isCrossCopy()
99 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
103 if (DstSubIdx) in isCrossCopy()
104 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
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| H A D | RegisterCoalescer.cpp | 1682 unsigned SrcSubIdx = 0, DstSubIdx = 0; in eliminateUndefCopy() local
1683 if(!isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) in eliminateUndefCopy()
1738 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx); in eliminateUndefCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5031 int DstSubIdx = DstIdx % ElemsPerVReg; in lowerShuffleViaVRegSplitting()
5046 OutMasks[DstVecIdx].second[DstSubIdx] = SrcSubIdx; in lowerShuffleViaVRegSplitting()
5030 int DstSubIdx = DstIdx % ElemsPerVReg; lowerShuffleViaVRegSplitting() local
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