Searched refs:DstSR (Results 1 – 1 of 1) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 219 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
646 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
665 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
668 .addReg(DstR, DstState, DstSR) in genCondTfrFor()
673 .addReg(DstR, DstState, DstSR) in genCondTfrFor()
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