Searched refs:DstRegClass (Results 1 – 4 of 4) sorted by relevance
3308 unsigned DstRegClass; in buildRegSequence32() local3312 DstRegClass = AMDGPU::VReg_256RegClassID; in buildRegSequence32()3316 DstRegClass = AMDGPU::VReg_128RegClassID; in buildRegSequence32()3320 DstRegClass = AMDGPU::VReg_64RegClassID; in buildRegSequence32()3328 Ops.push_back(CurDAG->getTargetConstant(DstRegClass, DL, MVT::i32)); in buildRegSequence32()
4939 const TargetRegisterClass *DstRegClass; in buildRegSequence() local4942 DstRegClass = &AMDGPU::VReg_256RegClass; in buildRegSequence()4945 DstRegClass = &AMDGPU::VReg_128RegClass; in buildRegSequence()4948 DstRegClass = &AMDGPU::VReg_64RegClass; in buildRegSequence()4956 .addDef(MRI.createVirtualRegister(DstRegClass)); in buildRegSequence()
5122 const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg); in lowerWaveReduce() local5124 Register ActiveLanes = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()5144 Register ParityRegister = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()5156 Register NegatedVal = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()5197 const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg); in lowerWaveReduce() local5199 Register InitalValReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()5201 Register AccumulatorReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()5205 Register FF1Reg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()
3708 int16_t DstRegClass = Desc.operands()[StartOp].RegClass; in expandMem16Inst() local3710 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); in expandMem16Inst()3836 int16_t DstRegClass = Desc.operands()[StartOp].RegClass; in expandMem9Inst() local3838 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); in expandMem9Inst()