Searched refs:DstRegClass (Results 1 – 4 of 4) sorted by relevance
3119 unsigned DstRegClass; in buildRegSequence32() local3123 DstRegClass = AMDGPU::VReg_256RegClassID; in buildRegSequence32()3127 DstRegClass = AMDGPU::VReg_128RegClassID; in buildRegSequence32()3131 DstRegClass = AMDGPU::VReg_64RegClassID; in buildRegSequence32()3139 Ops.push_back(CurDAG->getTargetConstant(DstRegClass, DL, MVT::i32)); in buildRegSequence32()
3906 const TargetRegisterClass *DstRegClass; in buildRegSequence() local3909 DstRegClass = &AMDGPU::VReg_256RegClass; in buildRegSequence()3912 DstRegClass = &AMDGPU::VReg_128RegClass; in buildRegSequence()3915 DstRegClass = &AMDGPU::VReg_64RegClass; in buildRegSequence()3923 .addDef(MRI.createVirtualRegister(DstRegClass)); in buildRegSequence()
4882 const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg); in lowerWaveReduce() local4884 Register InitalValReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()4886 Register AccumulatorReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()4890 Register FF1Reg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()4891 Register LaneValueReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()
3766 int16_t DstRegClass = Desc.operands()[StartOp].RegClass; in expandMem16Inst() local3768 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); in expandMem16Inst()3893 int16_t DstRegClass = Desc.operands()[StartOp].RegClass; in expandMem9Inst() local3895 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); in expandMem9Inst()