| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTfrCleanup.cpp | 184 unsigned DstR = MI->getOperand(0).getReg(); in rewriteIfImm() local
187 if (!isIntReg(DstR, Is32) || !isIntReg(SrcR, Tmp)) in rewriteIfImm()
201 NewMI = BuildMI(B, MI, DL, HII->get(A2_tfrsi), DstR).addImm(SVal); in rewriteIfImm()
203 NewMI = BuildMI(B, MI, DL, HII->get(A2_tfrpi), DstR).addImm(SVal); in rewriteIfImm()
205 NewMI = BuildMI(B, MI, DL, HII->get(A2_combineii), DstR) in rewriteIfImm()
212 NewMI = BuildMI(B, MI, DL, HII->get(CONST64), DstR).addImm(Val); in rewriteIfImm()
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| H A D | RDFCopy.cpp | 45 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy() local
47 assert(Register::isPhysicalRegister(DstR.Reg)); in interpretAsCopy()
50 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
53 if (!DFG.isTracked(SrcR) || !DFG.isTracked(DstR)) in interpretAsCopy()
55 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
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| H A D | HexagonFrameLowering.cpp | 1710 Register DstR = MI->getOperand(0).getReg(); in expandCopy() local
1712 if (!Hexagon::ModRegsRegClass.contains(DstR) || in expandCopy()
1718 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR) in expandCopy()
1768 Register DstR = MI->getOperand(0).getReg(); in expandLoadInt() local
1782 BuildMI(B, It, DL, HII.get(TfrOpc), DstR) in expandLoadInt()
1835 Register DstR = MI->getOperand(0).getReg(); in expandLoadVecPred() local
1852 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR) in expandLoadVecPred()
1933 Register DstR = MI->getOperand(0).getReg(); in expandLoadVec2() local
1934 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2()
1935 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2()
[all …]
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| H A D | HexagonRDFOpt.cpp | 111 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
112 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
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| H A D | HexagonExpandCondsets.cpp | 211 MachineBasicBlock::iterator At, unsigned DstR,
629 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
648 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
651 .addReg(DstR, DstState, DstSR) in genCondTfrFor()
656 .addReg(DstR, DstState, DstSR) in genCondTfrFor()
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| H A D | HexagonGenInsert.cpp | 525 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
666 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
668 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm()
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| H A D | HexagonSplitDouble.cpp | 994 Register DstR = MI->getOperand(0).getReg(); in splitInstr() local
995 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 703 const Register DstR = Dst.getReg(); in processInstructionForSlowLEA() local
706 if ((!SrcR1 || SrcR1 != DstR) && (!SrcR2 || SrcR2 != DstR)) in processInstructionForSlowLEA()
716 const MachineOperand &Src = SrcR1 == DstR ? Index : Base; in processInstructionForSlowLEA()
718 BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src); in processInstructionForSlowLEA()
725 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA()
726 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR) in processInstructionForSlowLEA()
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