| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 70 class DstOp {
79 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
80 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
81 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} in DstOp() function
82 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} in DstOp() function
83 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() function
228 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
456 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
468 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
480 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
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| H A D | CSEMIRBuilder.h | 56 void profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const;
58 void profileDstOps(ArrayRef<DstOp> Ops, GISelInstProfileBuilder &B) const { in profileDstOps()
59 for (const DstOp &Op : Ops) in profileDstOps()
72 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
82 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
88 bool checkCopyToDefsPossible(ArrayRef<DstOp> DstOps);
95 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
100 MachineInstrBuilder buildConstant(const DstOp &Res,
105 MachineInstrBuilder buildFConstant(const DstOp &Res,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 136 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res, in buildDynStackAlloc()
147 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res, in buildFrameIndex()
156 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res, in buildGlobalValue()
169 MachineInstrBuilder MachineIRBuilder::buildConstantPool(const DstOp &Res, in buildConstantPool()
202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, in buildPtrAdd()
227 MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res, in buildMaskLowPtrBits()
238 MachineIRBuilder::buildPadVectorWithUndefElements(const DstOp &Res, in buildPadVectorWithUndefElements()
269 MachineIRBuilder::buildDeleteTrailingVectorElements(const DstOp &Res, in buildDeleteTrailingVectorElements()
312 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy()
317 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
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| H A D | CSEMIRBuilder.cpp | 73 void CSEMIRBuilder::profileDstOp(const DstOp &Op, in profileDstOp()
76 case DstOp::DstType::Ty_RC: in profileDstOp()
79 case DstOp::DstType::Ty_Reg: { in profileDstOp()
113 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything()
137 bool CSEMIRBuilder::checkCopyToDefsPossible(ArrayRef<DstOp> DstOps) { in checkCopyToDefsPossible()
141 return llvm::all_of(DstOps, [](const DstOp &Op) { in checkCopyToDefsPossible()
142 DstOp::DstType DT = Op.getDstOpKind(); in checkCopyToDefsPossible()
143 return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC; in checkCopyToDefsPossible()
148 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps, in generateCopiesIfRequired()
153 const DstOp &Op = DstOps[0]; in generateCopiesIfRequired()
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| H A D | LegalizerHelper.cpp | 1014 DstOp Dest(MRI.createGenericVirtualRegister(MemTy)); in createResetStateLibcall()
4229 static void makeDstOps(SmallVectorImpl<DstOp> &DstOps, LLT Ty, in makeDstOps()
4292 SmallVector<SmallVector<DstOp, 8>, 2> OutputOpsPieces(NumDefs); in fewerElementsVectorMultiEltType()
4323 SmallVector<DstOp, 2> Defs; in fewerElementsVectorMultiEltType()
4357 SmallVector<DstOp, 8> OutputOpsPieces; in fewerElementsVectorPhi()
8182 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, in SwapN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.cpp | 224 Table.push_back({Entry.DstOp, Entry.KeyOp, in addTableEntry()
251 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
253 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
261 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
263 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
272 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
274 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
282 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
284 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
293 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
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| H A D | X86InstrFoldTables.h | 25 unsigned DstOp; member
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| H A D | X86FixupVectorConstants.cpp | 597 OpBcst32 = Mem2Bcst->DstOp; in processInstruction()
604 OpBcst64 = Mem2Bcst->DstOp; in processInstruction()
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| H A D | X86MCInstLower.cpp | 1467 const MachineOperand &DstOp = MI->getOperand(0); in printDstRegisterName() local
1468 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()); in printDstRegisterName()
1901 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
1902 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRDFOpt.cpp | 126 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
129 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
130 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
132 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
143 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
145 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
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| /freebsd/contrib/llvm-project/llvm/lib/Linker/ |
| H A D | IRMover.cpp | 1297 MDNode *DstOp; in linkModuleFlagsMetadata() local
1299 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1314 if (!DstOp) { in linkModuleFlagsMetadata()
1326 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1338 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1376 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1387 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1393 << *DstOp->getOperand(2) << "' from " << DstM.getModuleIdentifier() in linkModuleFlagsMetadata()
1401 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1408 (DstBehaviorValue != Module::Min ? SrcOp : DstOp)->getOperand(0), ID, in linkModuleFlagsMetadata()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstrInfo.cpp | 250 auto DstOp = I->getOperand(0); in copyPhysReg() local
252 assert(DstOp.isReg() && SrcOp.isReg() && in copyPhysReg()
255 MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg()); in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 88 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
90 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
91 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SelectionDAGInfo.cpp | 60 auto *DstOp = in EmitMOPS() local
70 DAG.setNodeMemRefs(Node, {DstOp}); in EmitMOPS()
80 DAG.setNodeMemRefs(Node, {DstOp, SrcOp}); in EmitMOPS()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 260 const MachineOperand &DstOp = MI.getOperand(0); in isCopyOf() local
264 if (DstOp.getSubReg() != SrcOp.getSubReg()) in isCopyOf()
266 if (DstOp.getReg() == Reg) in isCopyOf()
269 return DstOp.getReg(); in isCopyOf()
290 const MachineOperand &DstOp = *CopyInst->Destination; in isCopyOfBundle() local
292 if (DstOp.getReg() == Reg) { in isCopyOfBundle()
299 SnipReg = DstOp.getReg(); in isCopyOfBundle()
300 else if (SnipReg != DstOp.getReg()) in isCopyOfBundle()
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| H A D | MachineVerifier.cpp | 1908 const MachineOperand &DstOp = MI->getOperand(0); in verifyPreISelGenericInstruction() local
1912 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) { in verifyPreISelGenericInstruction()
2227 const MachineOperand &DstOp = MI->getOperand(0); in visitMachineInstrBefore() local
2230 const Register DstReg = DstOp.getReg(); in visitMachineInstrBefore()
2280 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
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| H A D | MachineScheduler.cpp | 2091 const MachineOperand &DstOp = Copy->getOperand(0); in constrainLocalCopy() local
2092 Register DstReg = DstOp.getReg(); in constrainLocalCopy()
2093 if (!DstReg.isVirtual() || DstOp.isDead()) in constrainLocalCopy()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MIRYamlMapping.h | 521 unsigned DstOp;
525 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
526 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
535 YamlIO.mapRequired("dstop", Sub.DstOp);
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 1511 Record *DstOp = Dst.getOperator(); in createInstructionRenderer() local
1512 if (!DstOp->isSubClassOf("Instruction")) { in createInstructionRenderer()
1513 if (DstOp->isSubClassOf("ValueType")) in createInstructionRenderer()
1518 CodeGenInstruction *DstI = &Target.getInstruction(DstOp); in createInstructionRenderer()
2014 Record *DstOp = Dst.getOperator(); in runOnPattern() local
2015 if (!DstOp->isSubClassOf("Instruction")) in runOnPattern()
2018 auto &DstI = Target.getInstruction(DstOp); in runOnPattern()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.cpp | 158 const DstOp &Res, Register Addr) { in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 675 buildDefaultVLOps(const DstOp &Dst, MachineIRBuilder &MIB, in buildDefaultVLOps()
685 buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo, in buildSplatPartsS64WithVL()
701 buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru, in buildSplatSplitS64WithVL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 283 MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy, in buildLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 472 {Sub.DstInst, Sub.DstOp}, Sub.Subreg); in setupDebugValueTracking()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 1351 DstOp(getLLTForType(*F.getType(), DL)).addDefToMIB(MRI, MIB); in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 928 ResolvedDbgOp DstOp(Dst); in transferMlocs() local
935 ActiveVLocIt->second.Ops.end(), SrcOp, DstOp); in transferMlocs()
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