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Searched refs:DstOp (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h71 class DstOp {
81 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
82 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
83 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} in DstOp() function
84 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} in DstOp() function
85 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() function
86 DstOp(MachineRegisterInfo::VRegAttrs Attrs) in DstOp() function
88 DstOp(RegClassOrRegBank RCOrRB, LLT Ty) in DstOp() function
240 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
468 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
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H A DCSEMIRBuilder.h63 void profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const;
65 void profileDstOps(ArrayRef<DstOp> Ops, GISelInstProfileBuilder &B) const { in profileDstOps()
66 for (const DstOp &Op : Ops) in profileDstOps()
79 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
89 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
95 bool checkCopyToDefsPossible(ArrayRef<DstOp> DstOps);
102 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
107 MachineInstrBuilder buildConstant(const DstOp &Res,
112 MachineInstrBuilder buildFConstant(const DstOp &Res,
H A DLegalizerHelper.h315 LLVM_ABI MachineInstrBuilder createStackStoreLoad(const DstOp &Res,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp136 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res, in buildDynStackAlloc()
147 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res, in buildFrameIndex()
156 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res, in buildGlobalValue()
169 MachineInstrBuilder MachineIRBuilder::buildConstantPool(const DstOp &Res, in buildConstantPool()
202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, in buildPtrAdd()
227 MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res, in buildMaskLowPtrBits()
238 MachineIRBuilder::buildPadVectorWithUndefElements(const DstOp &Res, in buildPadVectorWithUndefElements()
269 MachineIRBuilder::buildDeleteTrailingVectorElements(const DstOp &Res, in buildDeleteTrailingVectorElements()
312 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy()
317 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
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H A DCSEMIRBuilder.cpp71 void CSEMIRBuilder::profileDstOp(const DstOp &Op, in profileDstOp()
74 case DstOp::DstType::Ty_RC: { in profileDstOp()
78 case DstOp::DstType::Ty_Reg: { in profileDstOp()
83 case DstOp::DstType::Ty_LLT: { in profileDstOp()
87 case DstOp::DstType::Ty_VRegAttrs: { in profileDstOp()
117 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything()
141 bool CSEMIRBuilder::checkCopyToDefsPossible(ArrayRef<DstOp> DstOps) { in checkCopyToDefsPossible()
145 return llvm::all_of(DstOps, [](const DstOp &Op) { in checkCopyToDefsPossible()
146 DstOp::DstType DT = Op.getDstOpKind(); in checkCopyToDefsPossible()
147 return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC; in checkCopyToDefsPossible()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp189 for (const auto &[Idx, DstOp] : enumerate(Insn.Operands)) { in evaluateExpansion()
190 unsigned MIOpNo = DstOp.MIOperandNo; in evaluateExpansion()
193 if (!DstOp.MIOperandInfo || DstOp.MIOperandInfo->getNumArgs() == 0) in evaluateExpansion()
195 "', operand '" + DstOp.Rec->getName() + in evaluateExpansion()
197 if (DstOp.MINumOperands != SubDag->getNumArgs()) { in evaluateExpansion()
202 DstOp.Rec->getName() + "'"); in evaluateExpansion()
204 for (unsigned I = 0, E = DstOp.MINumOperands; I != E; ++I) { in evaluateExpansion()
205 auto *OpndRec = cast<DefInit>(DstOp.MIOperandInfo->getArg(I))->getDef(); in evaluateExpansion()
210 addOperandMapping(MIOpNo, DstOp.MINumOperands, Rec, Dag, Idx, DstOp.Rec, in evaluateExpansion()
H A DGlobalISelEmitter.cpp1513 const Record *DstOp = Dst.getOperator(); in createInstructionRenderer() local
1514 if (!DstOp->isSubClassOf("Instruction")) { in createInstructionRenderer()
1515 if (DstOp->isSubClassOf("ValueType")) in createInstructionRenderer()
1520 CodeGenInstruction *DstI = &Target.getInstruction(DstOp); in createInstructionRenderer()
1785 const Record *DstOp = Dst.getOperator(); in constrainOperands() local
1786 const CodeGenInstruction &DstI = Target.getInstruction(DstOp); in constrainOperands()
2147 const Record *DstOp = Dst.getOperator(); in runOnPattern() local
2148 if (!DstOp->isSubClassOf("Instruction")) in runOnPattern()
2151 const CodeGenInstruction &DstI = Target.getInstruction(DstOp); in runOnPattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFoldTables.cpp224 Table.push_back({Entry.DstOp, Entry.KeyOp, in addTableEntry()
251 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
253 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
261 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
263 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
272 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
274 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
282 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
284 unsigned MemOp = Reg2Mem->DstOp; in X86BroadcastFoldTable()
293 unsigned BcstOp = Reg2Bcst.DstOp; in X86BroadcastFoldTable()
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H A DX86InstrFoldTables.h25 unsigned DstOp; member
H A DX86MCInstLower.cpp1462 const MachineOperand &DstOp = MI->getOperand(0); in printDstRegisterName() local
1463 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()); in printDstRegisterName()
1931 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
1932 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
H A DX86FixupVectorConstants.cpp701 unsigned OpBcst = Mem2Bcst->DstOp; in processInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp119 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
122 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
123 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
136 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
138 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
/freebsd/contrib/llvm-project/llvm/lib/Linker/
H A DIRMover.cpp1189 MDNode *DstOp; in linkModuleFlagsMetadata() local
1191 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1206 if (!DstOp) { in linkModuleFlagsMetadata()
1218 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1230 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1267 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1278 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1284 << *DstOp->getOperand(2) << "' from " << DstM.getModuleIdentifier() in linkModuleFlagsMetadata()
1292 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1299 (DstBehaviorValue != Module::Min ? SrcOp : DstOp)->getOperand(0), ID, in linkModuleFlagsMetadata()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp281 auto DstOp = I->getOperand(0); in copyPhysReg() local
283 assert(DstOp.isReg() && SrcOp.isReg() && in copyPhysReg()
286 MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg()); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp89 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
91 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
92 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
H A DSIRegisterInfo.cpp2618 MachineOperand &DstOp = MI->getOperand(0); in eliminateFrameIndex() local
2619 Register DstReg = DstOp.getReg(); in eliminateFrameIndex()
2816 MachineOperand &DstOp = MI->getOperand(0); in eliminateFrameIndex() local
2827 if (OtherOp.isReg() && OtherOp.getReg() != DstOp.getReg()) in eliminateFrameIndex()
2828 TmpReg = DstOp.getReg(); in eliminateFrameIndex()
2863 Register DstReg = DstOp.getReg(); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp135 auto *DstOp = in EmitMOPS() local
145 DAG.setNodeMemRefs(Node, {DstOp}); in EmitMOPS()
155 DAG.setNodeMemRefs(Node, {DstOp, SrcOp}); in EmitMOPS()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DInlineSpiller.cpp259 const MachineOperand &DstOp = MI.getOperand(0); in isCopyOf() local
263 if (DstOp.getSubReg() != SrcOp.getSubReg()) in isCopyOf()
265 if (DstOp.getReg() == Reg) in isCopyOf()
268 return DstOp.getReg(); in isCopyOf()
289 const MachineOperand &DstOp = *CopyInst->Destination; in isCopyOfBundle() local
291 if (DstOp.getReg() == Reg) { in isCopyOfBundle()
298 SnipReg = DstOp.getReg(); in isCopyOfBundle()
299 else if (SnipReg != DstOp.getReg()) in isCopyOfBundle()
H A DMachineVerifier.cpp2028 const MachineOperand &DstOp = MI->getOperand(0); in verifyPreISelGenericInstruction() local
2032 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) { in verifyPreISelGenericInstruction()
2357 const MachineOperand &DstOp = MI->getOperand(0); in visitMachineInstrBefore() local
2360 const Register DstReg = DstOp.getReg(); in visitMachineInstrBefore()
2410 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
H A DMachineScheduler.cpp2364 const MachineOperand &DstOp = Copy->getOperand(0); in constrainLocalCopy() local
2365 Register DstReg = DstOp.getReg(); in constrainLocalCopy()
2366 if (!DstReg.isVirtual() || DstOp.isDead()) in constrainLocalCopy()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMIRYamlMapping.h524 unsigned DstOp;
528 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
529 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
538 YamlIO.mapRequired("dstop", Sub.DstOp);
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp155 const DstOp &Res, Register Addr) { in assignValueToAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp84 bool isMVEIntMACMatched(unsigned SrcOp, unsigned DstOp) { in isMVEIntMACMatched() argument
85 return SrcOp == DstOp || Info[DstOp].MVEIntMACMatched == SrcOp; in isMVEIntMACMatched()
H A DARMCallLowering.cpp283 MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy, in buildLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp980 buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo, in buildSplatPartsS64WithVL()
996 buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru, in buildSplatSplitS64WithVL()

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