| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCExpandAtomicPseudoInsts.cpp | 107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI() local
110 PairedCopy(TII, MBB, MI, MI.getDebugLoc(), DstHi, DstLo, Hi, Lo); in expandMI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
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| H A D | MipsSEInstrInfo.cpp | 717 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
719 LoInst.addReg(DstLo, RegState::Define); in expandPseudoMTLoHi()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 2021 auto DstLo = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
2070 MIRBuilder.buildExtract({DstLo}, {CASDst}, 0); in legalizeAtomicCmpxchg128()
2095 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
2106 MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1584 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); in applyMappingMAD_64_32() local
1587 MRI.setRegBank(DstLo, AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1644 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1646 MRI.setRegBank(DstLo, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1664 auto AddLo = B.buildUAddo(S32, CarryType, DstLo, Src2Lo); in applyMappingMAD_64_32()
1665 DstLo = AddLo.getReg(0); in applyMappingMAD_64_32()
1667 MRI.setRegBank(DstLo, DstBank); in applyMappingMAD_64_32()
1690 B.buildMergeLikeInstr(Dst0, {DstLo, DstHi}); in applyMappingMAD_64_32()
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| H A D | AMDGPUInstructionSelector.cpp | 370 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
374 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo) in selectG_ADD_SUB()
384 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_CO_U32_e64), DstLo) in selectG_ADD_SUB()
401 .addReg(DstLo) in selectG_ADD_SUB()
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| H A D | SIInstrInfo.cpp | 2186 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
2214 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
2236 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
2261 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
2266 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo) in expandPostRAPseudo()
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| H A D | SIISelLowering.cpp | 5294 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
5323 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in EmitInstrWithCustomInserter()
5337 .addReg(DstLo) in EmitInstrWithCustomInserter()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1948 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2() local
1959 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
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