Searched refs:DstLane (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 475 int DstLane; in matchINS() local
476 std::tie(DstIsLeft, DstLane) = *DstIsLeftAndDstLane; in matchINS()
482 int SrcLane = ShuffleMask[DstLane]; in matchINS()
488 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
499 int DstLane, SrcLane; in applyINS() local
500 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
503 auto DstCst = Builder.buildConstant(LLT::scalar(64), DstLane); in applyINS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 5235 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; in setExecutionDomain() local
5236 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); in setExecutionDomain()
5283 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
5287 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
5293 if (SrcLane == DstLane) in setExecutionDomain()
5301 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
5305 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
5311 if (SrcLane != DstLane) in setExecutionDomain()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 14786 int DstLane = i / NumEltsPerLane; in lowerShuffleAsLanePermuteAndPermute() local
14791 int DstSubStart = DstLane * NumSublanesPerLane; in lowerShuffleAsLanePermuteAndPermute()
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