1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 RegTupleAlignUnitsWidth = 2, 20 HasVGPRBit = RegTupleAlignUnitsWidth, 21 HasAGPRBit, 22 HasSGPRbit, 23 24 HasVGPR = 1 << HasVGPRBit, 25 HasAGPR = 1 << HasAGPRBit, 26 HasSGPR = 1 << HasSGPRbit, 27 28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1, 29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR) 30 }; // enum SIRCFlagsr 31 32 namespace SIEncodingFamily { 33 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td 34 // and the columns of the getMCOpcodeGen table. 35 enum { 36 SI = 0, 37 VI = 1, 38 SDWA = 2, 39 SDWA9 = 3, 40 GFX80 = 4, 41 GFX9 = 5, 42 GFX10 = 6, 43 SDWA10 = 7, 44 GFX90A = 8, 45 GFX940 = 9, 46 GFX11 = 10, 47 GFX12 = 11, 48 GFX1250 = 12, 49 }; 50 } 51 52 namespace SIInstrFlags { 53 // This needs to be kept in sync with the field bits in InstSI. 54 enum : uint64_t { 55 // Low bits - basic encoding information. 56 SALU = 1 << 0, 57 VALU = 1 << 1, 58 59 // SALU instruction formats. 60 SOP1 = 1 << 2, 61 SOP2 = 1 << 3, 62 SOPC = 1 << 4, 63 SOPK = 1 << 5, 64 SOPP = 1 << 6, 65 66 // VALU instruction formats. 67 VOP1 = 1 << 7, 68 VOP2 = 1 << 8, 69 VOPC = 1 << 9, 70 71 // TODO: Should this be spilt into VOP3 a and b? 72 VOP3 = 1 << 10, 73 VOP3P = 1 << 12, 74 75 VINTRP = 1 << 13, 76 SDWA = 1 << 14, 77 DPP = 1 << 15, 78 TRANS = 1 << 16, 79 80 // Memory instruction formats. 81 MUBUF = 1 << 17, 82 MTBUF = 1 << 18, 83 SMRD = 1 << 19, 84 MIMG = 1 << 20, 85 VIMAGE = 1 << 21, 86 VSAMPLE = 1 << 22, 87 EXP = 1 << 23, 88 FLAT = 1 << 24, 89 DS = 1 << 25, 90 91 // Combined SGPR/VGPR Spill bit 92 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill 93 Spill = 1 << 26, 94 95 // LDSDIR instruction format. 96 LDSDIR = 1 << 28, 97 98 // VINTERP instruction format. 99 VINTERP = 1 << 29, 100 101 VOPD3 = 1 << 30, 102 103 // High bits - other information. 104 VM_CNT = UINT64_C(1) << 32, 105 EXP_CNT = UINT64_C(1) << 33, 106 LGKM_CNT = UINT64_C(1) << 34, 107 108 WQM = UINT64_C(1) << 35, 109 DisableWQM = UINT64_C(1) << 36, 110 Gather4 = UINT64_C(1) << 37, 111 112 TENSOR_CNT = UINT64_C(1) << 38, 113 114 SCALAR_STORE = UINT64_C(1) << 39, 115 FIXED_SIZE = UINT64_C(1) << 40, 116 117 ASYNC_CNT = UINT64_C(1) << 41, 118 119 VOP3_OPSEL = UINT64_C(1) << 42, 120 maybeAtomic = UINT64_C(1) << 43, 121 renamedInGFX9 = UINT64_C(1) << 44, 122 123 // Is a clamp on FP type. 124 FPClamp = UINT64_C(1) << 45, 125 126 // Is an integer clamp 127 IntClamp = UINT64_C(1) << 46, 128 129 // Clamps lo component of register. 130 ClampLo = UINT64_C(1) << 47, 131 132 // Clamps hi component of register. 133 // ClampLo and ClampHi set for packed clamp. 134 ClampHi = UINT64_C(1) << 48, 135 136 // Is a packed VOP3P instruction. 137 IsPacked = UINT64_C(1) << 49, 138 139 // Is a D16 buffer instruction. 140 D16Buf = UINT64_C(1) << 50, 141 142 // FLAT instruction accesses FLAT_GLBL segment. 143 FlatGlobal = UINT64_C(1) << 51, 144 145 // Uses floating point double precision rounding mode 146 FPDPRounding = UINT64_C(1) << 52, 147 148 // Instruction is FP atomic. 149 FPAtomic = UINT64_C(1) << 53, 150 151 // Is a MFMA instruction. 152 IsMAI = UINT64_C(1) << 54, 153 154 // Is a DOT instruction. 155 IsDOT = UINT64_C(1) << 55, 156 157 // FLAT instruction accesses FLAT_SCRATCH segment. 158 FlatScratch = UINT64_C(1) << 56, 159 160 // Atomic without return. 161 IsAtomicNoRet = UINT64_C(1) << 57, 162 163 // Atomic with return. 164 IsAtomicRet = UINT64_C(1) << 58, 165 166 // Is a WMMA instruction. 167 IsWMMA = UINT64_C(1) << 59, 168 169 // Whether tied sources will be read. 170 TiedSourceNotRead = UINT64_C(1) << 60, 171 172 // Is never uniform. 173 IsNeverUniform = UINT64_C(1) << 61, 174 175 // ds_gws_* instructions. 176 GWS = UINT64_C(1) << 62, 177 178 // Is a SWMMAC instruction. 179 IsSWMMAC = UINT64_C(1) << 63, 180 }; 181 182 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 183 // The result is true if any of these tests are true. 184 enum ClassFlags : unsigned { 185 S_NAN = 1 << 0, // Signaling NaN 186 Q_NAN = 1 << 1, // Quiet NaN 187 N_INFINITY = 1 << 2, // Negative infinity 188 N_NORMAL = 1 << 3, // Negative normal 189 N_SUBNORMAL = 1 << 4, // Negative subnormal 190 N_ZERO = 1 << 5, // Negative zero 191 P_ZERO = 1 << 6, // Positive zero 192 P_SUBNORMAL = 1 << 7, // Positive subnormal 193 P_NORMAL = 1 << 8, // Positive normal 194 P_INFINITY = 1 << 9 // Positive infinity 195 }; 196 } 197 198 namespace AMDGPU { 199 enum OperandType : unsigned { 200 /// Operands with register or 32-bit immediate 201 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 202 OPERAND_REG_IMM_INT64, 203 OPERAND_REG_IMM_INT16, 204 OPERAND_REG_IMM_FP32, 205 OPERAND_REG_IMM_FP64, 206 OPERAND_REG_IMM_BF16, 207 OPERAND_REG_IMM_FP16, 208 OPERAND_REG_IMM_V2BF16, 209 OPERAND_REG_IMM_V2FP16, 210 OPERAND_REG_IMM_V2INT16, 211 OPERAND_REG_IMM_V2INT32, 212 OPERAND_REG_IMM_V2FP32, 213 214 /// Operands with register or inline constant 215 OPERAND_REG_INLINE_C_INT16, 216 OPERAND_REG_INLINE_C_INT32, 217 OPERAND_REG_INLINE_C_INT64, 218 OPERAND_REG_INLINE_C_BF16, 219 OPERAND_REG_INLINE_C_FP16, 220 OPERAND_REG_INLINE_C_FP32, 221 OPERAND_REG_INLINE_C_FP64, 222 OPERAND_REG_INLINE_C_V2INT16, 223 OPERAND_REG_INLINE_C_V2BF16, 224 OPERAND_REG_INLINE_C_V2FP16, 225 226 // Operand for split barrier inline constant 227 OPERAND_INLINE_SPLIT_BARRIER_INT32, 228 229 /// Operand with 32-bit immediate that uses the constant bus. 230 OPERAND_KIMM32, 231 OPERAND_KIMM16, 232 OPERAND_KIMM64, 233 234 /// Operands with an AccVGPR register or inline constant 235 OPERAND_REG_INLINE_AC_INT32, 236 OPERAND_REG_INLINE_AC_FP32, 237 OPERAND_REG_INLINE_AC_FP64, 238 239 // Operand for source modifiers for VOP instructions 240 OPERAND_INPUT_MODS, 241 242 // Operand for SDWA instructions 243 OPERAND_SDWA_VOPC_DST, 244 245 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 246 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 247 248 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 249 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64, 250 251 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32, 252 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_FP64, 253 254 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 255 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 256 257 OPERAND_KIMM_FIRST = OPERAND_KIMM32, 258 OPERAND_KIMM_LAST = OPERAND_KIMM64 259 260 }; 261 } 262 263 // Input operand modifiers bit-masks 264 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 265 namespace SISrcMods { 266 enum : unsigned { 267 NONE = 0, 268 NEG = 1 << 0, // Floating-point negate modifier 269 ABS = 1 << 1, // Floating-point absolute modifier 270 SEXT = 1 << 4, // Integer sign-extend modifier 271 NEG_HI = ABS, // Floating-point negate high packed component modifier. 272 OP_SEL_0 = 1 << 2, 273 OP_SEL_1 = 1 << 3, 274 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 275 }; 276 } 277 278 namespace SIOutMods { 279 enum : unsigned { 280 NONE = 0, 281 MUL2 = 1, 282 MUL4 = 2, 283 DIV2 = 3 284 }; 285 } 286 287 namespace AMDGPU { 288 namespace VGPRIndexMode { 289 290 enum Id : unsigned { // id of symbolic names 291 ID_SRC0 = 0, 292 ID_SRC1, 293 ID_SRC2, 294 ID_DST, 295 296 ID_MIN = ID_SRC0, 297 ID_MAX = ID_DST 298 }; 299 300 enum EncBits : unsigned { 301 OFF = 0, 302 SRC0_ENABLE = 1 << ID_SRC0, 303 SRC1_ENABLE = 1 << ID_SRC1, 304 SRC2_ENABLE = 1 << ID_SRC2, 305 DST_ENABLE = 1 << ID_DST, 306 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 307 UNDEF = 0xFFFF 308 }; 309 310 } // namespace VGPRIndexMode 311 } // namespace AMDGPU 312 313 namespace AMDGPUAsmVariants { 314 enum : unsigned { 315 DEFAULT = 0, 316 VOP3 = 1, 317 SDWA = 2, 318 SDWA9 = 3, 319 DPP = 4, 320 VOP3_DPP = 5 321 }; 322 } // namespace AMDGPUAsmVariants 323 324 namespace AMDGPU { 325 namespace EncValues { // Encoding values of enum9/8/7 operands 326 327 enum : unsigned { 328 SGPR_MIN = 0, 329 SGPR_MAX_SI = 101, 330 SGPR_MAX_GFX10 = 105, 331 TTMP_VI_MIN = 112, 332 TTMP_VI_MAX = 123, 333 TTMP_GFX9PLUS_MIN = 108, 334 TTMP_GFX9PLUS_MAX = 123, 335 INLINE_INTEGER_C_MIN = 128, 336 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 337 INLINE_INTEGER_C_MAX = 208, 338 INLINE_FLOATING_C_MIN = 240, 339 INLINE_FLOATING_C_MAX = 248, 340 LITERAL64_CONST = 254, 341 LITERAL_CONST = 255, 342 VGPR_MIN = 256, 343 VGPR_MAX = 511, 344 IS_VGPR = 256, // Indicates VGPR or AGPR 345 }; 346 347 } // namespace EncValues 348 349 // Register codes as defined in the TableGen's HWEncoding field. 350 namespace HWEncoding { 351 enum : unsigned { 352 REG_IDX_MASK = 0xff, 353 IS_VGPR = 1 << 8, 354 IS_AGPR = 1 << 9, 355 IS_HI16 = 1 << 10, 356 }; 357 } // namespace HWEncoding 358 359 namespace CPol { 360 361 enum CPol { 362 GLC = 1, 363 SLC = 2, 364 DLC = 4, 365 SCC = 16, 366 SC0 = GLC, 367 SC1 = SCC, 368 NT = SLC, 369 ALL_pregfx12 = GLC | SLC | DLC | SCC, 370 SWZ_pregfx12 = 8, 371 372 // Below are GFX12+ cache policy bits 373 374 // Temporal hint 375 TH = 0x7, // All TH bits 376 TH_RT = 0, // regular 377 TH_NT = 1, // non-temporal 378 TH_HT = 2, // high-temporal 379 TH_LU = 3, // last use 380 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL) 381 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL) 382 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL) 383 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL) 384 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL) 385 TH_BYPASS = 3, // only to be used with scope = 3 386 387 TH_RESERVED = 7, // unused value for load insts 388 389 // Bits of TH for atomics 390 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning 391 TH_ATOMIC_NT = SLC, // Non-temporal vs regular 392 TH_ATOMIC_CASCADE = 4, // Cascading vs regular 393 394 // Scope 395 SCOPE = 0x3 << 3, // All Scope bits 396 SCOPE_CU = 0 << 3, 397 SCOPE_SE = 1 << 3, 398 SCOPE_DEV = 2 << 3, 399 SCOPE_SYS = 3 << 3, 400 401 SWZ = 1 << 6, // Swizzle bit 402 403 ALL = TH | SCOPE, 404 405 // Helper bits 406 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy 407 TH_TYPE_STORE = 1 << 8, // TH_STORE policy 408 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy 409 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not 410 411 // Volatile (used to preserve/signal operation volatility for buffer 412 // operations not a real instruction bit) 413 VOLATILE = 1 << 31, 414 }; 415 416 } // namespace CPol 417 418 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 419 420 enum Id { // Message ID, width(4) [3:0]. 421 ID_INTERRUPT = 1, 422 423 ID_GS_PreGFX11 = 2, // replaced in GFX11 424 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11 425 426 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11 427 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11 428 429 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11 430 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12 431 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12 432 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11 433 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 434 ID_GS_ALLOC_REQ = 9, // added in GFX9 435 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11 436 ID_GET_DDID = 11, // added in GFX10, removed in GFX11 437 ID_SYSMSG = 15, 438 439 ID_RTN_GET_DOORBELL = 128, 440 ID_RTN_GET_DDID = 129, 441 ID_RTN_GET_TMA = 130, 442 ID_RTN_GET_REALTIME = 131, 443 ID_RTN_SAVE_WAVE = 132, 444 ID_RTN_GET_TBA = 133, 445 ID_RTN_GET_TBA_TO_PC = 134, 446 ID_RTN_GET_SE_AID_ID = 135, 447 448 ID_MASK_PreGFX11_ = 0xF, 449 ID_MASK_GFX11Plus_ = 0xFF 450 }; 451 452 enum Op { // Both GS and SYS operation IDs. 453 OP_SHIFT_ = 4, 454 OP_NONE_ = 0, 455 // Bits used for operation encoding 456 OP_WIDTH_ = 3, 457 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 458 // GS operations are encoded in bits 5:4 459 OP_GS_NOP = 0, 460 OP_GS_CUT = 1, 461 OP_GS_EMIT = 2, 462 OP_GS_EMIT_CUT = 3, 463 OP_GS_FIRST_ = OP_GS_NOP, 464 // SYS operations are encoded in bits 6:4 465 OP_SYS_ECC_ERR_INTERRUPT = 1, 466 OP_SYS_REG_RD = 2, 467 OP_SYS_HOST_TRAP_ACK = 3, 468 OP_SYS_TTRACE_PC = 4, 469 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 470 }; 471 472 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 473 STREAM_ID_NONE_ = 0, 474 STREAM_ID_DEFAULT_ = 0, 475 STREAM_ID_LAST_ = 4, 476 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 477 STREAM_ID_SHIFT_ = 8, 478 STREAM_ID_WIDTH_= 2, 479 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 480 }; 481 482 } // namespace SendMsg 483 484 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 485 486 enum Id { // HwRegCode, (6) [5:0] 487 ID_MODE = 1, 488 ID_STATUS = 2, 489 ID_TRAPSTS = 3, 490 ID_HW_ID = 4, 491 ID_GPR_ALLOC = 5, 492 ID_LDS_ALLOC = 6, 493 ID_IB_STS = 7, 494 ID_PERF_SNAPSHOT_DATA_gfx12 = 10, 495 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11, 496 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12, 497 ID_MEM_BASES = 15, 498 ID_TBA_LO = 16, 499 ID_TBA_HI = 17, 500 ID_TMA_LO = 18, 501 ID_TMA_HI = 19, 502 ID_FLAT_SCR_LO = 20, 503 ID_FLAT_SCR_HI = 21, 504 ID_XNACK_MASK = 22, 505 ID_HW_ID1 = 23, 506 ID_HW_ID2 = 24, 507 ID_POPS_PACKER = 25, 508 ID_PERF_SNAPSHOT_DATA_gfx11 = 27, 509 ID_SHADER_CYCLES = 29, 510 ID_SHADER_CYCLES_HI = 30, 511 ID_DVGPR_ALLOC_LO = 31, 512 ID_DVGPR_ALLOC_HI = 32, 513 514 // Register numbers reused in GFX11 515 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18, 516 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19, 517 518 // Register numbers reused in GFX12+ 519 ID_STATE_PRIV = 4, 520 ID_PERF_SNAPSHOT_DATA1 = 15, 521 ID_PERF_SNAPSHOT_DATA2 = 16, 522 ID_EXCP_FLAG_PRIV = 17, 523 ID_EXCP_FLAG_USER = 18, 524 ID_TRAP_CTRL = 19, 525 526 // GFX94* specific registers 527 ID_XCC_ID = 20, 528 ID_SQ_PERF_SNAPSHOT_DATA = 21, 529 ID_SQ_PERF_SNAPSHOT_DATA1 = 22, 530 ID_SQ_PERF_SNAPSHOT_PC_LO = 23, 531 ID_SQ_PERF_SNAPSHOT_PC_HI = 24, 532 }; 533 534 enum Offset : unsigned { // Offset, (5) [10:6] 535 OFFSET_MEM_VIOL = 8, 536 OFFSET_ME_ID = 8, // in HW_ID2 537 }; 538 539 enum ModeRegisterMasks : uint32_t { 540 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 541 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 542 DX10_CLAMP_MASK = 1 << 8, 543 IEEE_MODE_MASK = 1 << 9, 544 LOD_CLAMP_MASK = 1 << 10, 545 DEBUG_MASK = 1 << 11, 546 547 // EXCP_EN fields. 548 EXCP_EN_INVALID_MASK = 1 << 12, 549 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 550 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 551 EXCP_EN_OVERFLOW_MASK = 1 << 15, 552 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 553 EXCP_EN_INEXACT_MASK = 1 << 17, 554 EXCP_EN_INT_DIV0_MASK = 1 << 18, 555 556 GPR_IDX_EN_MASK = 1 << 27, 557 VSKIP_MASK = 1 << 28, 558 CSP_MASK = 0x7u << 29 // Bits 29..31 559 }; 560 561 } // namespace Hwreg 562 563 namespace MTBUFFormat { 564 565 enum DataFormat : int64_t { 566 DFMT_INVALID = 0, 567 DFMT_8, 568 DFMT_16, 569 DFMT_8_8, 570 DFMT_32, 571 DFMT_16_16, 572 DFMT_10_11_11, 573 DFMT_11_11_10, 574 DFMT_10_10_10_2, 575 DFMT_2_10_10_10, 576 DFMT_8_8_8_8, 577 DFMT_32_32, 578 DFMT_16_16_16_16, 579 DFMT_32_32_32, 580 DFMT_32_32_32_32, 581 DFMT_RESERVED_15, 582 583 DFMT_MIN = DFMT_INVALID, 584 DFMT_MAX = DFMT_RESERVED_15, 585 586 DFMT_UNDEF = -1, 587 DFMT_DEFAULT = DFMT_8, 588 589 DFMT_SHIFT = 0, 590 DFMT_MASK = 0xF 591 }; 592 593 enum NumFormat : int64_t { 594 NFMT_UNORM = 0, 595 NFMT_SNORM, 596 NFMT_USCALED, 597 NFMT_SSCALED, 598 NFMT_UINT, 599 NFMT_SINT, 600 NFMT_RESERVED_6, // VI and GFX9 601 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 602 NFMT_FLOAT, 603 604 NFMT_MIN = NFMT_UNORM, 605 NFMT_MAX = NFMT_FLOAT, 606 607 NFMT_UNDEF = -1, 608 NFMT_DEFAULT = NFMT_UNORM, 609 610 NFMT_SHIFT = 4, 611 NFMT_MASK = 7 612 }; 613 614 enum MergedFormat : int64_t { 615 DFMT_NFMT_UNDEF = -1, 616 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 617 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 618 619 620 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 621 622 DFMT_NFMT_MAX = DFMT_NFMT_MASK 623 }; 624 625 enum UnifiedFormatCommon : int64_t { 626 UFMT_MAX = 127, 627 UFMT_UNDEF = -1, 628 UFMT_DEFAULT = 1 629 }; 630 631 } // namespace MTBUFFormat 632 633 namespace UfmtGFX10 { 634 enum UnifiedFormat : int64_t { 635 UFMT_INVALID = 0, 636 637 UFMT_8_UNORM, 638 UFMT_8_SNORM, 639 UFMT_8_USCALED, 640 UFMT_8_SSCALED, 641 UFMT_8_UINT, 642 UFMT_8_SINT, 643 644 UFMT_16_UNORM, 645 UFMT_16_SNORM, 646 UFMT_16_USCALED, 647 UFMT_16_SSCALED, 648 UFMT_16_UINT, 649 UFMT_16_SINT, 650 UFMT_16_FLOAT, 651 652 UFMT_8_8_UNORM, 653 UFMT_8_8_SNORM, 654 UFMT_8_8_USCALED, 655 UFMT_8_8_SSCALED, 656 UFMT_8_8_UINT, 657 UFMT_8_8_SINT, 658 659 UFMT_32_UINT, 660 UFMT_32_SINT, 661 UFMT_32_FLOAT, 662 663 UFMT_16_16_UNORM, 664 UFMT_16_16_SNORM, 665 UFMT_16_16_USCALED, 666 UFMT_16_16_SSCALED, 667 UFMT_16_16_UINT, 668 UFMT_16_16_SINT, 669 UFMT_16_16_FLOAT, 670 671 UFMT_10_11_11_UNORM, 672 UFMT_10_11_11_SNORM, 673 UFMT_10_11_11_USCALED, 674 UFMT_10_11_11_SSCALED, 675 UFMT_10_11_11_UINT, 676 UFMT_10_11_11_SINT, 677 UFMT_10_11_11_FLOAT, 678 679 UFMT_11_11_10_UNORM, 680 UFMT_11_11_10_SNORM, 681 UFMT_11_11_10_USCALED, 682 UFMT_11_11_10_SSCALED, 683 UFMT_11_11_10_UINT, 684 UFMT_11_11_10_SINT, 685 UFMT_11_11_10_FLOAT, 686 687 UFMT_10_10_10_2_UNORM, 688 UFMT_10_10_10_2_SNORM, 689 UFMT_10_10_10_2_USCALED, 690 UFMT_10_10_10_2_SSCALED, 691 UFMT_10_10_10_2_UINT, 692 UFMT_10_10_10_2_SINT, 693 694 UFMT_2_10_10_10_UNORM, 695 UFMT_2_10_10_10_SNORM, 696 UFMT_2_10_10_10_USCALED, 697 UFMT_2_10_10_10_SSCALED, 698 UFMT_2_10_10_10_UINT, 699 UFMT_2_10_10_10_SINT, 700 701 UFMT_8_8_8_8_UNORM, 702 UFMT_8_8_8_8_SNORM, 703 UFMT_8_8_8_8_USCALED, 704 UFMT_8_8_8_8_SSCALED, 705 UFMT_8_8_8_8_UINT, 706 UFMT_8_8_8_8_SINT, 707 708 UFMT_32_32_UINT, 709 UFMT_32_32_SINT, 710 UFMT_32_32_FLOAT, 711 712 UFMT_16_16_16_16_UNORM, 713 UFMT_16_16_16_16_SNORM, 714 UFMT_16_16_16_16_USCALED, 715 UFMT_16_16_16_16_SSCALED, 716 UFMT_16_16_16_16_UINT, 717 UFMT_16_16_16_16_SINT, 718 UFMT_16_16_16_16_FLOAT, 719 720 UFMT_32_32_32_UINT, 721 UFMT_32_32_32_SINT, 722 UFMT_32_32_32_FLOAT, 723 UFMT_32_32_32_32_UINT, 724 UFMT_32_32_32_32_SINT, 725 UFMT_32_32_32_32_FLOAT, 726 727 UFMT_FIRST = UFMT_INVALID, 728 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 729 }; 730 731 } // namespace UfmtGFX10 732 733 namespace UfmtGFX11 { 734 enum UnifiedFormat : int64_t { 735 UFMT_INVALID = 0, 736 737 UFMT_8_UNORM, 738 UFMT_8_SNORM, 739 UFMT_8_USCALED, 740 UFMT_8_SSCALED, 741 UFMT_8_UINT, 742 UFMT_8_SINT, 743 744 UFMT_16_UNORM, 745 UFMT_16_SNORM, 746 UFMT_16_USCALED, 747 UFMT_16_SSCALED, 748 UFMT_16_UINT, 749 UFMT_16_SINT, 750 UFMT_16_FLOAT, 751 752 UFMT_8_8_UNORM, 753 UFMT_8_8_SNORM, 754 UFMT_8_8_USCALED, 755 UFMT_8_8_SSCALED, 756 UFMT_8_8_UINT, 757 UFMT_8_8_SINT, 758 759 UFMT_32_UINT, 760 UFMT_32_SINT, 761 UFMT_32_FLOAT, 762 763 UFMT_16_16_UNORM, 764 UFMT_16_16_SNORM, 765 UFMT_16_16_USCALED, 766 UFMT_16_16_SSCALED, 767 UFMT_16_16_UINT, 768 UFMT_16_16_SINT, 769 UFMT_16_16_FLOAT, 770 771 UFMT_10_11_11_FLOAT, 772 773 UFMT_11_11_10_FLOAT, 774 775 UFMT_10_10_10_2_UNORM, 776 UFMT_10_10_10_2_SNORM, 777 UFMT_10_10_10_2_UINT, 778 UFMT_10_10_10_2_SINT, 779 780 UFMT_2_10_10_10_UNORM, 781 UFMT_2_10_10_10_SNORM, 782 UFMT_2_10_10_10_USCALED, 783 UFMT_2_10_10_10_SSCALED, 784 UFMT_2_10_10_10_UINT, 785 UFMT_2_10_10_10_SINT, 786 787 UFMT_8_8_8_8_UNORM, 788 UFMT_8_8_8_8_SNORM, 789 UFMT_8_8_8_8_USCALED, 790 UFMT_8_8_8_8_SSCALED, 791 UFMT_8_8_8_8_UINT, 792 UFMT_8_8_8_8_SINT, 793 794 UFMT_32_32_UINT, 795 UFMT_32_32_SINT, 796 UFMT_32_32_FLOAT, 797 798 UFMT_16_16_16_16_UNORM, 799 UFMT_16_16_16_16_SNORM, 800 UFMT_16_16_16_16_USCALED, 801 UFMT_16_16_16_16_SSCALED, 802 UFMT_16_16_16_16_UINT, 803 UFMT_16_16_16_16_SINT, 804 UFMT_16_16_16_16_FLOAT, 805 806 UFMT_32_32_32_UINT, 807 UFMT_32_32_32_SINT, 808 UFMT_32_32_32_FLOAT, 809 UFMT_32_32_32_32_UINT, 810 UFMT_32_32_32_32_SINT, 811 UFMT_32_32_32_32_FLOAT, 812 813 UFMT_FIRST = UFMT_INVALID, 814 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 815 }; 816 817 } // namespace UfmtGFX11 818 819 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 820 821 enum Id : unsigned { // id of symbolic names 822 ID_QUAD_PERM = 0, 823 ID_BITMASK_PERM, 824 ID_SWAP, 825 ID_REVERSE, 826 ID_BROADCAST, 827 ID_FFT, 828 ID_ROTATE 829 }; 830 831 // clang-format off 832 enum EncBits : unsigned { 833 834 // swizzle mode encodings 835 836 QUAD_PERM_ENC = 0x8000, 837 QUAD_PERM_ENC_MASK = 0xFF00, 838 839 BITMASK_PERM_ENC = 0x0000, 840 BITMASK_PERM_ENC_MASK = 0x8000, 841 842 FFT_MODE_ENC = 0xE000, 843 844 ROTATE_MODE_ENC = 0xC000, 845 FFT_ROTATE_MODE_MASK = 0xF000, 846 847 ROTATE_MODE_LO = 0xC000, 848 FFT_MODE_LO = 0xE000, 849 850 // QUAD_PERM encodings 851 852 LANE_MASK = 0x3, 853 LANE_MAX = LANE_MASK, 854 LANE_SHIFT = 2, 855 LANE_NUM = 4, 856 857 // BITMASK_PERM encodings 858 859 BITMASK_MASK = 0x1F, 860 BITMASK_MAX = BITMASK_MASK, 861 BITMASK_WIDTH = 5, 862 863 BITMASK_AND_SHIFT = 0, 864 BITMASK_OR_SHIFT = 5, 865 BITMASK_XOR_SHIFT = 10, 866 867 // FFT encodings 868 869 FFT_SWIZZLE_MASK = 0x1F, 870 FFT_SWIZZLE_MAX = 0x1F, 871 872 // ROTATE encodings 873 ROTATE_MAX_SIZE = 0x1F, 874 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction 875 ROTATE_DIR_MASK = 0x1, 876 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size 877 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE, 878 }; 879 // clang-format on 880 881 } // namespace Swizzle 882 883 namespace SDWA { 884 885 enum SdwaSel : unsigned { 886 BYTE_0 = 0, 887 BYTE_1 = 1, 888 BYTE_2 = 2, 889 BYTE_3 = 3, 890 WORD_0 = 4, 891 WORD_1 = 5, 892 DWORD = 6, 893 }; 894 895 enum DstUnused : unsigned { 896 UNUSED_PAD = 0, 897 UNUSED_SEXT = 1, 898 UNUSED_PRESERVE = 2, 899 }; 900 901 enum SDWA9EncValues : unsigned { 902 SRC_SGPR_MASK = 0x100, 903 SRC_VGPR_MASK = 0xFF, 904 VOPC_DST_VCC_MASK = 0x80, 905 VOPC_DST_SGPR_MASK = 0x7F, 906 907 SRC_VGPR_MIN = 0, 908 SRC_VGPR_MAX = 255, 909 SRC_SGPR_MIN = 256, 910 SRC_SGPR_MAX_SI = 357, 911 SRC_SGPR_MAX_GFX10 = 361, 912 SRC_TTMP_MIN = 364, 913 SRC_TTMP_MAX = 379, 914 }; 915 916 } // namespace SDWA 917 918 namespace DPP { 919 920 // clang-format off 921 enum DppCtrl : unsigned { 922 QUAD_PERM_FIRST = 0, 923 QUAD_PERM_ID = 0xE4, // identity permutation 924 QUAD_PERM_LAST = 0xFF, 925 DPP_UNUSED1 = 0x100, 926 ROW_SHL0 = 0x100, 927 ROW_SHL_FIRST = 0x101, 928 ROW_SHL_LAST = 0x10F, 929 DPP_UNUSED2 = 0x110, 930 ROW_SHR0 = 0x110, 931 ROW_SHR_FIRST = 0x111, 932 ROW_SHR_LAST = 0x11F, 933 DPP_UNUSED3 = 0x120, 934 ROW_ROR0 = 0x120, 935 ROW_ROR_FIRST = 0x121, 936 ROW_ROR_LAST = 0x12F, 937 WAVE_SHL1 = 0x130, 938 DPP_UNUSED4_FIRST = 0x131, 939 DPP_UNUSED4_LAST = 0x133, 940 WAVE_ROL1 = 0x134, 941 DPP_UNUSED5_FIRST = 0x135, 942 DPP_UNUSED5_LAST = 0x137, 943 WAVE_SHR1 = 0x138, 944 DPP_UNUSED6_FIRST = 0x139, 945 DPP_UNUSED6_LAST = 0x13B, 946 WAVE_ROR1 = 0x13C, 947 DPP_UNUSED7_FIRST = 0x13D, 948 DPP_UNUSED7_LAST = 0x13F, 949 ROW_MIRROR = 0x140, 950 ROW_HALF_MIRROR = 0x141, 951 BCAST15 = 0x142, 952 BCAST31 = 0x143, 953 DPP_UNUSED8_FIRST = 0x144, 954 DPP_UNUSED8_LAST = 0x14F, 955 ROW_NEWBCAST_FIRST= 0x150, 956 ROW_NEWBCAST_LAST = 0x15F, 957 ROW_SHARE0 = 0x150, 958 ROW_SHARE_FIRST = 0x150, 959 ROW_SHARE_LAST = 0x15F, 960 ROW_XMASK0 = 0x160, 961 ROW_XMASK_FIRST = 0x160, 962 ROW_XMASK_LAST = 0x16F, 963 DPP_LAST = ROW_XMASK_LAST 964 }; 965 // clang-format on 966 967 enum DppFiMode { 968 DPP_FI_0 = 0, 969 DPP_FI_1 = 1, 970 DPP8_FI_0 = 0xE9, 971 DPP8_FI_1 = 0xEA, 972 }; 973 974 } // namespace DPP 975 976 namespace Exp { 977 978 enum Target : unsigned { 979 ET_MRT0 = 0, 980 ET_MRT7 = 7, 981 ET_MRTZ = 8, 982 ET_NULL = 9, // Pre-GFX11 983 ET_POS0 = 12, 984 ET_POS3 = 15, 985 ET_POS4 = 16, // GFX10+ 986 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 987 ET_PRIM = 20, // GFX10+ 988 ET_DUAL_SRC_BLEND0 = 21, // GFX11+ 989 ET_DUAL_SRC_BLEND1 = 22, // GFX11+ 990 ET_PARAM0 = 32, // Pre-GFX11 991 ET_PARAM31 = 63, // Pre-GFX11 992 993 ET_NULL_MAX_IDX = 0, 994 ET_MRTZ_MAX_IDX = 0, 995 ET_PRIM_MAX_IDX = 0, 996 ET_MRT_MAX_IDX = 7, 997 ET_POS_MAX_IDX = 4, 998 ET_DUAL_SRC_BLEND_MAX_IDX = 1, 999 ET_PARAM_MAX_IDX = 31, 1000 1001 ET_INVALID = 255, 1002 }; 1003 1004 } // namespace Exp 1005 1006 namespace VOP3PEncoding { 1007 1008 enum OpSel : uint64_t { 1009 OP_SEL_HI_0 = UINT64_C(1) << 59, 1010 OP_SEL_HI_1 = UINT64_C(1) << 60, 1011 OP_SEL_HI_2 = UINT64_C(1) << 14, 1012 }; 1013 1014 } // namespace VOP3PEncoding 1015 1016 namespace ImplicitArg { 1017 // Implicit kernel argument offset for code object version 5. 1018 enum Offset_COV5 : unsigned { 1019 HOSTCALL_PTR_OFFSET = 80, 1020 MULTIGRID_SYNC_ARG_OFFSET = 88, 1021 HEAP_PTR_OFFSET = 96, 1022 1023 DEFAULT_QUEUE_OFFSET = 104, 1024 COMPLETION_ACTION_OFFSET = 112, 1025 1026 PRIVATE_BASE_OFFSET = 192, 1027 SHARED_BASE_OFFSET = 196, 1028 QUEUE_PTR_OFFSET = 200, 1029 }; 1030 1031 } // namespace ImplicitArg 1032 1033 namespace MFMAScaleFormats { 1034 // Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix 1035 // format. 1036 enum MFMAScaleFormats { 1037 FP8_E4M3 = 0, 1038 FP8_E5M2 = 1, 1039 FP6_E2M3 = 2, 1040 FP6_E3M2 = 3, 1041 FP4_E2M1 = 4 1042 }; 1043 } // namespace MFMAScaleFormats 1044 1045 namespace VirtRegFlag { 1046 // Virtual register flags used for various target specific handlings during 1047 // codegen. 1048 enum Register_Flag : uint8_t { 1049 // Register operand in a whole-wave mode operation. 1050 WWM_REG = 1 << 0, 1051 }; 1052 1053 } // namespace VirtRegFlag 1054 1055 } // namespace AMDGPU 1056 1057 namespace AMDGPU { 1058 namespace Barrier { 1059 1060 enum Type { TRAP = -2, WORKGROUP = -1 }; 1061 1062 enum { 1063 BARRIER_SCOPE_WORKGROUP = 0, 1064 }; 1065 1066 } // namespace Barrier 1067 } // namespace AMDGPU 1068 1069 // clang-format off 1070 1071 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 1072 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 1073 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 1074 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 1075 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 1076 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 1077 1078 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 1079 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 1080 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 1081 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 1082 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 1083 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 1084 1085 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 1086 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 1087 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 1088 #define C_00B228_WGP_MODE 0xF7FFFFFF 1089 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 1090 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 1091 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 1092 1093 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 1094 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 1095 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 1096 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 1097 #define C_00B428_WGP_MODE 0xFBFFFFFF 1098 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 1099 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 1100 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 1101 1102 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 1103 1104 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 1105 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 1106 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 1107 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 1108 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 1109 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 1110 #define C_00B84C_USER_SGPR 0xFFFFFFC1 1111 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 1112 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 1113 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 1114 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 1115 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 1116 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 1117 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 1118 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 1119 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 1120 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 1121 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 1122 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 1123 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 1124 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 1125 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 1126 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 1127 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 1128 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 1129 /* CIK */ 1130 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 1131 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 1132 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 1133 /* */ 1134 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 1135 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 1136 #define C_00B84C_LDS_SIZE 0xFF007FFF 1137 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 1138 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 1139 #define C_00B84C_EXCP_EN 0x80FFFFFF 1140 1141 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 1142 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 1143 1144 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 1145 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 1146 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 1147 #define C_00B848_VGPRS 0xFFFFFFC0 1148 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 1149 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 1150 #define C_00B848_SGPRS 0xFFFFFC3F 1151 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 1152 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 1153 #define C_00B848_PRIORITY 0xFFFFF3FF 1154 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 1155 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 1156 #define C_00B848_FLOAT_MODE 0xFFF00FFF 1157 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 1158 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 1159 #define C_00B848_PRIV 0xFFEFFFFF 1160 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 1161 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 1162 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 1163 #define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21) 1164 #define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1) 1165 #define C_00B848_RR_WG_MODE 0xFFDFFFFF 1166 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 1167 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 1168 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 1169 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 1170 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 1171 #define C_00B848_IEEE_MODE 0xFF7FFFFF 1172 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 1173 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 1174 #define C_00B848_WGP_MODE 0xDFFFFFFF 1175 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 1176 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 1177 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 1178 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 1179 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 1180 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 1181 1182 // Helpers for setting FLOAT_MODE 1183 #define FP_ROUND_ROUND_TO_NEAREST 0 1184 #define FP_ROUND_ROUND_TO_INF 1 1185 #define FP_ROUND_ROUND_TO_NEGINF 2 1186 #define FP_ROUND_ROUND_TO_ZERO 3 1187 1188 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 1189 // precision. 1190 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 1191 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 1192 1193 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 1194 #define FP_DENORM_FLUSH_OUT 1 1195 #define FP_DENORM_FLUSH_IN 2 1196 #define FP_DENORM_FLUSH_NONE 3 1197 1198 1199 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 1200 // precision. 1201 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 1202 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 1203 1204 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 1205 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) 1206 #define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12) 1207 #define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12) 1208 1209 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 1210 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) 1211 #define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12) 1212 #define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12) 1213 1214 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 1215 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 1216 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 1217 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 1218 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 1219 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 1220 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 1221 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 1222 1223 #define R_SPILLED_SGPRS 0x4 1224 #define R_SPILLED_VGPRS 0x8 1225 1226 // clang-format on 1227 1228 } // End namespace llvm 1229 1230 #endif 1231