Searched refs:DppCtrl (Results 1 – 5 of 5) sorted by relevance
1075 if (Imm <= DppCtrl::QUAD_PERM_LAST) { in printDPPCtrl()1081 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && in printDPPCtrl()1082 (Imm <= DppCtrl::ROW_SHL_LAST)) { in printDPPCtrl()1085 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && in printDPPCtrl()1086 (Imm <= DppCtrl::ROW_SHR_LAST)) { in printDPPCtrl()1089 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && in printDPPCtrl()1090 (Imm <= DppCtrl::ROW_ROR_LAST)) { in printDPPCtrl()1093 } else if (Imm == DppCtrl::WAVE_SHL1) { in printDPPCtrl()1099 } else if (Imm == DppCtrl::WAVE_ROL1) { in printDPPCtrl()1105 } else if (Imm == DppCtrl::WAVE_SHR1) { in printDPPCtrl()[all …]
543 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl); in combineDPPMov() local544 assert(DppCtrl && DppCtrl->isImm()); in combineDPPMov()545 if (!AMDGPU::isLegalDPALU_DPPControl(DppCtrl->getImm())) { in combineDPPMov()
5204 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 || in verifyInstruction()5205 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST || in verifyInstruction()5206 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) || in verifyInstruction()5207 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) || in verifyInstruction()5208 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) || in verifyInstruction()5209 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) || in verifyInstruction()5210 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) { in verifyInstruction()5214 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 && in verifyInstruction()5220 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 && in verifyInstruction()5226 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST && in verifyInstruction()[all …]
914 enum DppCtrl : unsigned { enum
4606 unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm(); in validateDPP() local4608 if (!AMDGPU::isLegalDPALU_DPPControl(DppCtrl) && in validateDPP()8922 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) || in isDPPCtrl()8923 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) || in isDPPCtrl()8924 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) || in isDPPCtrl()8925 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) || in isDPPCtrl()8926 (Imm == DppCtrl::WAVE_SHL1) || in isDPPCtrl()8927 (Imm == DppCtrl::WAVE_ROL1) || in isDPPCtrl()8928 (Imm == DppCtrl::WAVE_SHR1) || in isDPPCtrl()8929 (Imm == DppCtrl::WAVE_ROR1) || in isDPPCtrl()[all …]