Searched refs:DivScale1 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5139 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}) in legalizeFDIV64() local
5146 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64()
5147 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64()
5159 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64()
5167 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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| H A D | SIISelLowering.cpp | 11482 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local
11485 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
11488 DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Mul, DivScale1); in LowerFDIV64()
11502 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64()
11518 Scale = DivScale1.getValue(1); in LowerFDIV64()
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