Searched refs:DivS1 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankLegalizeRules.cpp | 131 case DivS1: in matchUniformityAndLLT()
477 .Any({{DivS1}, {{Vcc}, {Vcc, Vcc}}}) in RegBankLegalizeRules()
528 addRulesForGOpcs({G_FREEZE}).Any({{DivS1}, {{Vcc}, {Vcc}}}); in RegBankLegalizeRules()
532 .Any({{DivS1, _, S32}, {{Vcc}, {None, Vgpr32, Vgpr32}}}); in RegBankLegalizeRules()
536 .Any({{DivS1, _, S32}, {{Vcc}, {None, Vgpr32, Vgpr32}}}); in RegBankLegalizeRules()
540 .Any({{DivS1}, {{}, {Vcc}}}); in RegBankLegalizeRules()
577 .Any({{DivS1, DivS16}, {{Vcc}, {Vgpr16}, VgprToVccCopy}}) in RegBankLegalizeRules()
578 .Any({{DivS1, DivS32}, {{Vcc}, {Vgpr32}, VgprToVccCopy}}) in RegBankLegalizeRules()
579 .Any({{DivS1, DivS64}, {{Vcc}, {Vgpr64}, VgprToVccCopy}}); in RegBankLegalizeRules()
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| H A D | AMDGPURegBankLegalizeRules.h | 54 DivS1, enumerator
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