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Searched refs:DispatchID (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.cpp70 << " DispatchID: " << FI.second.DispatchID in print()
129 return std::tuple(DispatchID ? &DispatchID : nullptr, in getPreloadedValue()
164 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
H A DSIMachineFunctionInfo.cpp228 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
231 return ArgInfo.DispatchID.getRegister(); in addDispatchID()
681 Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID); in convertArgumentInfo()
H A DAMDGPUArgumentUsageInfo.h138 ArgDescriptor DispatchID; member
H A DGCNSubtarget.h1734 bool hasDispatchID() const { return DispatchID; } in hasDispatchID()
1800 bool DispatchID = false; variable
H A DSIMachineFunctionInfo.h170 std::optional<SIArgument> DispatchID;
195 YamlIO.mapOptional("dispatchID", AI.DispatchID);
H A DGCNSubtarget.cpp625 DispatchID = true; in GCNUserSGPRUsageInfo()
H A DAMDGPUTargetMachine.cpp1926 parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID, in parseMachineFunctionInfo()
1927 AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID, in parseMachineFunctionInfo()
H A DSIISelLowering.cpp2518 allocateSGPR64Input(CCInfo, ArgInfo.DispatchID); in allocateSpecialInputSGPRs()