Searched refs:DestSubReg (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRangeEdit.cpp | 311 unsigned DestSubReg; in eliminateDeadDef() local
318 DestSubReg = MI->getOperand(0).getSubReg(); in eliminateDeadDef()
402 if (DestSubReg) { in eliminateDeadDef()
405 Alloc, TRI->getSubRegIndexLaneMask(DestSubReg)); in eliminateDeadDef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600MachineScheduler.cpp | 249 unsigned DestSubReg = MI->getOperand(0).getSubReg(); in getAluKind() local
250 switch (DestSubReg) { in getAluKind()
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| H A D | SIInstrInfo.cpp | 770 Register DestSubReg = RI.getSubReg(DestReg, SubIdx); in expandSGPRCopy() local
772 assert(DestSubReg && SrcSubReg && "Failed to find subregs!"); in expandSGPRCopy()
776 bool AlignedDest = ((DestSubReg - AMDGPU::SGPR0) % 2) == 0; in expandSGPRCopy()
782 DestSubReg = RI.getSubReg(DestReg, SubIdx); in expandSGPRCopy()
784 assert(DestSubReg && SrcSubReg && "Failed to find subregs!"); in expandSGPRCopy()
789 LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), DestSubReg) in expandSGPRCopy()
1127 Register DestSubReg = RI.getSubReg(DestReg, SubIdx); in copyPhysReg() local
1129 assert(DestSubReg && SrcSubReg && "Failed to find subregs!"); in copyPhysReg()
1137 indirectCopyToAGPR(*this, MBB, MI, DL, DestSubReg, SrcSubReg, UseKill, in copyPhysReg()
1141 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg) in copyPhysReg()
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