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Searched refs:DestSub1 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp8300 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
8301 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
8304 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp()
8310 .addReg(DestSub1) in splitScalar64BitUnaryOp()
8335 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulU64() local
8409 BuildMI(MBB, MII, DL, get(AMDGPU::V_ADD_U32_e32), DestSub1) in splitScalarSMulU64()
8416 .addReg(DestSub1) in splitScalarSMulU64()
8444 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulPseudo() local
8475 BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L); in splitScalarSMulPseudo()
8485 .addReg(DestSub1) in splitScalarSMulPseudo()
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H A DSILoadStoreOptimizer.cpp2021 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local
2032 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
2046 .addReg(DestSub1) in computeBase()
H A DSIISelLowering.cpp5350 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
5367 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()
5373 .addReg(DestSub1) in EmitInstrWithCustomInserter()
5406 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
5443 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()
5453 .addReg(DestSub1) in EmitInstrWithCustomInserter()